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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
OCTOBER 2003 REV. 2.0.4
GENERAL DESCRIPTION
The XRT73L03A, 3-Channel, DS3/E3/STS-1 Line Interface Unit is an improved version of the XRT73L03 and consists of three independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications. Each channel of the XRT73L03A can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. Each channel can be configured to operate in a mode/data rate that is independent of the other channels. In the transmit direction, each channel encodes input data to either B3ZS (DS3/STS-1) or HDB3 (E3) format and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer. In the receive direction, the XRT73L03A performs equalization on incoming signals, performs Clock Recovery, decodes data from either B3ZS or HDB3 format, converts the receive data into TTL/CMOS format, checks for LOS or LOL conditions and detects and declares the occurrence of Line Code Violations.
FEATURES * Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L03 * Meets E3/DS3/STS-1 Jitter Tolerance Requirements * Contains a 4-Wire Microprocessor Serial Interface * Full Loop-Back Capability * Transmit and Receive Power Down Modes * Full Redundancy Support * Uses Minimum External components * Single +3.3V Power Supply * 5V tolerant I/O * -40C to +85C Operating Temperature Range * Available in a Thermally Enhanced 120 pin TQFP package APPLICATIONS * Digital Cross Connect Systems * CSU/DSU Equipment * Routers * Fiber Optic Terminals * Multiplexers * ATM Switches
FIGURE 1. XRT73L03A BLOCK DIAGRAM
E3_(n) STS-1/DS3_(n) Host/(HW) RLOL_(n) EXClk_(n) RxOFF RxClkINV
RTIP_(n) RRing_(n) REQEN_(n)
AGC/ Equalizer Peak Detector
Slicer
Clock Recovery Data Recovery
Invert
RxClk_(n)
LOSTHR_(n) SDI SDO SClk CS REGR Serial Processor Interface
LOS Detector
HDB3/ B3ZS Decoder
RPOS_(n) RNEG_(n) LCV_(n) ENDECDIS RLOS_(n) LLB_(n) RLB_(n) TAOS_(n)
Loop MUX
TTIP_(n) Pulse Shaping TRing_(n) MTIP_(n) MRing_(n) DMO_(n) Tx Control
HDB3/ B3ZS Encoder
Transmit Logic Duty Cycle Adjust
TPData_(n) TNData_(n) TxClk_(n) TxLEV_(n) TxOFF_(n)
Device Monitor
Channel 0 - (n) = 0 Channel 1 - (n) = 1 Channel 2 - (n) = 2
Notes: 1. (n) = 0, 1, or 2 for respective Channels 2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
TYPICAL APPLICATIONS FIGURE 2. MULTICHANNEL ATM APPLICATION
RPOS RNEG RxClk RPOS RNEG RxClk
RPOS RNEG RxLineClk
RRPOS RRNEG RRClk
RTIP RRing
ATM Switch/ SAR
XRT72L73
TPOS TNEG TxLineClk
XRT71D03
MClk
XRT73L03
TPOS TNEG TxClk
TTIP TRing
3 Channel DS3 ATM UNI
3 Channel E3/DS3 J/A
3 Channel E3/DS3 LIU
FIGURE 3. MULTISERVICE - FRAME RELAY APPLICATION
RPOS RNEG RxLineClk
RRPOS RRNEG RRClk
RPOS RNEG RxClk
RPOS RNEG RxClk
RTIP RRing
Frame Relay
XRT72L56
TPOS TNEG TxLineClk
XRT71D03
MClk
XRT73L03
TPOS TNEG TxClk
TTIP TRing
6 Channel E3/DS3 Framer
2 x 3 Channel E3/DS3 J/A
2 x 3 Channel E3/DS3 LIU
TRANSMIT INTERFACE CHARACTERISTICS: * Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal from the line * Integrated Pulse Shaping Circuit * Built-in B3ZS/HDB3 Encoder (which can be disabled) * Contains Transmit Clock Duty Cycle Correction Circuit on-chip * Generates pulses that comply with the ITU-T G.703 pulse template (E3 applications) * Generates pulses that comply with the DSX-3 pulse template as specified in Bellcore GR-499-CORE and ANSI T1.102_1993 * Generates pulses that comply with the STSX-1 pulse template as specified in Bellcore GR-253CORE * Transmitter can be turned off in order to support redundancy designs
RECEIVE INTERFACE CHARACTERISTICS: * Integrated Adaptive Receive Equalization (optional) and Timing Recovery * Declares and Clears the LOS defect per ITU-T G.775 requirements (E3 and DS3 applications) * Meets Jitter Tolerance Requirements as specified in ITU-T G.823_1993 (E3 Applications) * Meets Jitter Tolerance Requirements as specified in Bellcore GR-499-CORE (DS3 Applications) * Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms * Built-in B3ZS/HDB3 Decoder (which can be disabled) * Recovered Data can be muted while the LOS Condition is declared * Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment * Receiver can be powered down in order to conserve power in redundancy designs
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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
FIGURE 4. PIN OUT OF THE XRT73L03A IN THE 120 PIN TQFP PACKAGE
REGR/(RxClkINV) STS-1/DS3_1 AGND_2 SR/(DR) E3_1 NC NC LOSTHR_1 LLB_1 RLB_1 RxAVDD_1 RRing_1 RTIP_1 RxAGND_1 REQEN_1 RxAGND_2 RTIP_2 RRing_2 RxAVDD_2 RLB_2 LLB_2 LOSTHR_2 REQEN_0 RxAGND_0 RTIP_0 RRing_0 RxAVDD_0 RLB_0 LLB_0 LOSTHR_0 ICT STS-1/DS3_0 SDO/(E3_0) SDI/(RxOFF_0) SClk/(RxOFF_1) CS/(ENDECDIS) 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
EXDGND EXDVDD EXClk_1 REQEN_2 STS1/DS3_2 E3_2 EXClk_2 RxOFF_2 RLOL_1 LCV_1 RLOS_1 RxDGND_1 RPOS_1 RNEG_1 RxClk_1 LOSMUTEN RxDVDD_1 AGND_1 TxOFF_2 TxOFF_1 TxOFF_0 TxAGND_1 TxAVDD_1 DMO_1
XRT73L03A
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
RLOL_2 LCV_2 RLOS_2 RLOL_0 LCV_0 RLOS_0 RxDGND_0 NC NC RPOS_0 RNEG_0 RxClk_0 RxDVDD_0 EXClk_0 RxDGND_2 RPOS_2 RNEG_2 RxClk_2 HOST/(HW) RxDVDD_2 AGND_0 TxAGND_0 DMO_0 TxAVDD_0
ORDERING INFORMATION
PART # XRT73L03AIV PACKAGE 120 Pin TQFP 14mm X 20mm OPERATING TEMPERATURE RANGE -40oC to +85oC
TNData_1 TPData_1 TxClk_1 MRing_1 MTIP_1 TAOS_1 TAOS_2 TxLEV_1 TxLEV_2 TTIP_1 TxAVDD_1 TRing_1 TxAGND_1 TxAGND_2 MRing_2 MTIP_2 TxAGND_2 TRing_2 TxAVDD_2 TTIP_2 DMO_2 TxAVDD_2 TNData_2 TPData_2 TxClk_2 TxAGND_0 TRing_0 TxAVDD_0 TTIP_0 MTIP_0 MRing_0 TNData_0 TPData_0 TxClk_0 TxLEV_0 TAOS_0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
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XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
FEATURES .................................................................................................................................................... APPLICATIONS ......................................................................................................................................... TYPICAL APPLICATIONS ................................................................................................................................. TRANSMIT INTERFACE CHARACTERISTICS: ..................................................................................................... RECEIVE INTERFACE CHARACTERISTICS: ....................................................................................................... 1 1 2 2 2
ORDERING INFORMATION ............................................................................................... 3 PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4
TRANSMIT INTERFACE ................................................................................................................................... 4 RECEIVE INTERFACE ..................................................................................................................................... 6 CLOCK INTERFACE ........................................................................................................................................ 7 OPERATING MODE SELECT ........................................................................................................................... 7 CONTROL AND ALARM INTERFACE ................................................................................................................. 9 MICROPROCESSOR INTERFACE .................................................................................................................... 11 POWER AND GROUND PINS ......................................................................................................................... 13 NO CONNECTION PINS ................................................................................................................................ 14
ELECTRICAL CHARACTERISTICS ................................................................................ 15
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15
SYSTEM DESCRIPTION .................................................................................................. 24
THE TRANSMIT SECTION - CHANNELS 0, 1 AND 2 ......................................................................................... THE RECEIVE SECTION - CHANNELS 0, 1 AND 2 ........................................................................................... THE MICROPROCESSOR SERIAL INTERFACE ................................................................................................. 1.0 Selecting the Data Rate .................................................................................................................... 24 24 24 25
1.1 CONFIGURING CHANNEL(N) ............................................................................................................................... 25
2.0 The Transmit Section ....................................................................................................................... 27 COMMAND REGISTER, CR4-(N) ...................................................................................................... 27
2.1 THE TRANSMIT LOGIC BLOCK ............................................................................................................................ 27 2.1.1 Accepting Dual-Rail Data from the Terminal Equipment ...................................................................... 27 2.1.2 Accepting Single-Rail Data from the Terminal Equipment ................................................................... 28
COMMAND REGISTER CR1-(N) ....................................................................................................... 28
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ................................................................................... 2.3 THE HDB3/B3ZS ENCODER BLOCK .................................................................................................................. 2.3.1 B3ZS Encoding .................................................................................................................................... 2.3.2 HDB3 Encoding .................................................................................................................................... 2.3.3 Disabling the HDB3/B3ZS Encoder ..................................................................................................... 29 29 29 30 30
COMMAND REGISTER CR2-(N) ....................................................................................................... 30
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY ....................................................................................................... 31 2.4.1 Enabling the Transmit Line Build-Out Circuit ....................................................................................... 32
COMMAND REGISTER, CR1-(N) ...................................................................................................... 32
2.4.2 Disabling the Transmit Line Build-Out Circuit ....................................................................................... 32
COMMAND REGISTER, CR1-(N) ...................................................................................................... 33
2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit ......................................................... 33 2.4.4 The Transmit Line Build-Out Circuit and E3 Applications .................................................................... 33 2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73L03A TO THE LINE ......................................................... 33
TRANSFORMER RECOMMENDATIONS ............................................................................................... 34 3.0 The Receive Section ......................................................................................................................... 35
3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L03A TO THE LINE ........................................................... 35 3.2 THE RECEIVE EQUALIZER BLOCK ...................................................................................................................... 36 3.2.1 Guidelines for Setting the Receive Equalizer ...................................................................................... 37
COMMAND REGISTER CR2-(N) ....................................................................................................... 38
3.3 CLOCK RECOVERY PLL .................................................................................................................................... 38 3.3.1 The Training Mode ............................................................................................................................... 39 3.3.2 The Data/Clock Recovery Mode .......................................................................................................... 39
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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
3.4 THE HDB3/B3ZS DECODER ............................................................................................................................. 3.4.1 B3ZS Decoding (DS3/STS-1 Applications) .......................................................................................... 3.4.2 HDB3 Decoding (E3 Applications) ....................................................................................................... 3.4.3 Configuring the HDB3/B3ZS Decoder .................................................................................................
39 39 39 40
COMMAND REGISTER CR2-(N) ...................................................................................................... 40
3.5 LOS DECLARATION/CLEARANCE ....................................................................................................................... 40 3.5.1 The LOS Declaration/Clearance Criteria for E3 Applications ............................................................... 41 3.5.2 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications .......................................... 42
COMMAND COMMAND COMMAND COMMAND
REGISTER CR0-(N) REGISTER CR2-(N) REGISTER CR0-(N) REGISTER CR2-(N)
...................................................................................................... ...................................................................................................... ...................................................................................................... ......................................................................................................
43 43 43 43
3.5.3 Muting the Recovered Data while the LOS is being Declared ............................................................. 43
COMMAND REGISTER CR3-(N) ...................................................................................................... 44
3.6 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT .............. 44 3.6.1 Routing Dual-Rail Format Data to the Receiving Terminal Equipment ................................................ 44
COMMAND REGISTER CR3-(N) ...................................................................................................... 46
3.6.2 Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment .............. 46
COMMAND REGISTER CR3-(N) ...................................................................................................... 46
3.7 SHUTTING OFF THE RECEIVE SECTION ............................................................................................................. 47
COMMAND REGISTER CR3-(N) ...................................................................................................... 47 4.0 Diagnostic Features of the XRT73L03A ......................................................................................... 48
4.1 THE ANALOG LOCAL LOOP-BACK MODE ............................................................................................................ 48 4.2 THE DIGITAL LOCAL LOOP-BACK MODE. ........................................................................................................... 49
COMMAND REGISTER CR4-(N) ...................................................................................................... 49 COMMAND REGISTER CR4-(N) ...................................................................................................... 49
4.3 THE REMOTE LOOP-BACK MODE ...................................................................................................................... 50
COMMAND REGISTER CR4-(n) ...................................................................................................... 50
4.4 TXOFF FEATURES ........................................................................................................................................... 51
COMMAND REGISTER CR1-(N) ...................................................................................................... 51
4.5 THE TRANSMIT DRIVE MONITOR FEATURES ....................................................................................................... 51 4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE .................................................................................................... 52
5.0 The Microprocessor Serial Interface .............................................................................................. 52
5.1 DESCRIPTION OF THE COMMAND REGISTERS .................................................................................................... 52
COMMAND REGISTER CR1-(N) ...................................................................................................... 52
5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER ........................................................................... 54 5.2.1 Command Register - CR0-(n) .............................................................................................................. 54
COMMAND REGISTER CR0-(N) ....................................................................................................... 54 COMMAND REGISTER CR1-(N) ...................................................................................................... 54
5.2.3 Command Register CR2-(n) ................................................................................................................ 55
COMMAND REGISTER CR2-(N) ...................................................................................................... 55 COMMAND REGISTER CR3-(N) ...................................................................................................... 55 COMMAND REGISTER CR4-(N) ...................................................................................................... 56
5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ................................................................................... 57
ORDERING INFORMATION ............................................................................................. 59 PACKAGE DIMENSIONS ................................................................................................. 59
REVISION HISTORY ..................................................................................................................................... 60 REV # ........................................................................................................................................... 60
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XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
PIN # 29 10 20 27 12 18 34 3 25 NAME TTIP_0 TTIP_1 TTIP_2 TRing_0 TRing_1 TRing_2 TxClk_0 TxClk_1 TxClk_2 TYPE O DESCRIPTION
Transmit TTIP Output - Channel (n):
The XRT73L03A uses this pin along with TRing_(n) to transmit a bipolar line signal via a 1:1 transformer.
O
Transmit Ring Output - Channel (n):
The XRT73L03A uses this pin along with TTIP_(n) to transmit a bipolar line signal via a 1:1 transformer.
I
Transmit Clock Input for TPData and TNData - Channel (n):
This input pin must be driven at 34.368 MHz for E3 applications, 44.736 MHz for DS3 applications, or 51.84 MHz for SONET STS-1 applications. The XRT73L03A uses this signal to sample the TPData_(n) and TNData_(n) input pins. By default, the XRT73L03A is configured to sample these two pins on the falling edge of this signal. NOTE: If the XRT73L03A is operating in the HOST Mode, then the device can be configured to sample the TPData_(n) and TNData_(n) input pins on either the rising or falling edge of TxClk_(n).
33 2 24
TPData_0 TPData_1 TPData_2
I
Transmit Positive Data Input - Channel (n):
The XRT73L03A samples this pin on the falling edge of TxClk_(n). If the device samples a "1", then it generates and transmits a positive polarity pulse to the line. The data should be applied to this input pin if the Transmit Section is configured to accept Single-Rail data from the Terminal Equipment. NOTE: If the XRT73L03A is operating in the HOST Mode, then the XRT73L03A can be configured to sample the TPData_(n) pin on either the rising or falling edge of TxClk_(n).
32 1 23
TNData_0 TNData_1 TNData_2
I
Transmit Negative Data Input - Channel (n):
The XRT73L03A samples this pin on the falling edge of TxClk_(n). If the device samples a "1", then it generates and transmits a negative polarity pulse to the line. In Single-Rail Mode, this pin must be tied to GND to enable the HDB3/ B3ZS Encoder and Decoder, (internally pulled-down). In Dual-Rail Mode this input is the N-Rail Data input. NOTE: If the XRT73L03A is operating in the HOST Mode, then the XRT73L03A can be configured to sample the TNData_(n) pin on either the rising or falling edge of TxClk_(n).
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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
TRANSMIT INTERFACE
PIN # 35 8 9 NAME TxLEV_0 TxLEV_1 TxLEV_2 TYPE I DESCRIPTION Transmit Line Build-Out Enable/Disable Select - Channel (n): This input pin permits the Transmit Line Build-Out circuit within Channel (n) to be enabled or disabled. In E3 mode, this pin has no effect on the transmit pulse shape. Setting this pin to "High" disables the Line Build-Out circuit. In this mode, Channel (n) outputs partially-shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. Setting this pin to "Low" enables the Line Build-Out circuit within Channel (n). In this mode, Channel (n) outputs shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. To comply with the Isolated DSX-3/STSX-1 Pulse Template Requirements per Bellcore GR-499-CORE or Bellcore GR-253-CORE: a. Set this input pin to "1" if the cable length between the CrossConnect and the transmit output of Channel (n) is greater than 225 feet. b. Set this input pin to "0" if the cable length between the CrossConnect and the transmit output of Channel (n) is less than 225 feet. This pin is active only if the following two conditions are true: a. The XRT73L03A is configured to operate in either the DS3 or SONET STS-1 Modes. b. The XRT73L03A is configured to operate in the Hardware Mode. NOTE: This pin to should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode, (internally pulled-down).
117 116 115
TxOFF_0 TxOFF_1 TxOFF_2
I
Transmitter OFF Input - Channel (n):
Setting this input pin "High" turns off all of the Transmitter Sections. In this mode the TTIP and TRing outputs are tri-stated. NOTES: 1. This input pin controls the TTIP and TRing outputs even when the XRT73L03A is operating in the HOST Mode. 2. For HOST Mode Operation, this pin is tied to GND if the Transmitter is intended to be turned off via the Microprocessor Serial Interface.
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XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
RECEIVE INTERFACE
PIN # 49 111 43 NAME RxClk_0 RxClk_1 RxClk_2 TYPE O DESCRIPTION Receive Clock Output - Channel (n): This output pin is the Recovered Clock signal from the incoming line signal for Channel (n). The Receive Section of Channel (n) outputs data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of this clock signal. Configure the Receive Section of Channel (n) to update the data on the RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n) by doing one of the following: a. Operating in the Hardware Mode Pull the RxClkINV pin to "High".
b. Operating in the HOST Mode
Write a "1" into the RxClkINV bit-field within the Command Register. 50 110 44 RNEG_0 RNEG_1 RNEG_2 O Receive Negative Data Output - Channel (n): This output pin pulses "High" whenever Channel (n) of the XRT73L03A has received a Negative Polarity pulse in the incoming line signal at the RTIP_(n)/RRing_(n) inputs.
NOTE: If the Channel (n) B3ZS/HDB3 Decoder is enabled, then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not reflected at this output.
51 109 45 RPOS_0 RPOS_1 RPOS_2 O Receive Positive Data Output - Channel (n): This output pin pulses "High" whenever Channel (n) of the XRT73L03A has received a Positive Polarity pulse in the incoming line signal at the RTIP_(n)/RRing_(n) inputs.
NOTE: If the Channel (n) B3ZS/HDB3 Decoder is enabled, then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not reflected at this output.
71 85 79 72 84 80 74 82 100 RRing_0 RRing_1 RRing_2 RTIP_0 RTIP_1 RTIP_2 REQEN_0 REQEN_1 REQEN_2 I
Receive Ring Input - Channel (n):
This input pin along with RTIP_(n) is used to receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal.
I
Receive TIP Input - Channel (n):
This input pin along with RRing_(n) is used to receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal.
I
Receive Equalization Enable Input - Channel (n): Setting this input pin "High" enables the Internal Receive Equalizer within Channel (n). Setting this pin "Low" disables the Internal Receive Equalizer. The guidelines for enabling and disabling the Receive Equalizer are described in Section 3.2. NOTE: This pin is ignored and should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode, (internally pulled-down).
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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
RECEIVE INTERFACE
PIN # 96 NAME REGR/ RxClkINV TYPE I DESCRIPTION Register Reset Input (Invert RxClk(n)) Output - Select: The function of this pin depends upon whether the XRT73L03A is operating in the HOST Mode or in the Hardware Mode.
NOTE: This pin is internally pulled "High".
In the HOST-Mode - Register Reset Input: Setting this input pin "Low" causes the XRT73L03A to reset the contents of the Command Registers to their default settings and default operating configuration. In the Hardware Mode - Invert RxClk Output Select: Setting this input pin "High" configures the Receive Section of all Channels in the XRT73L03A to invert their RxClk_(n) clock output signals and configures Channel (n) to output the recovered data via the RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n). Setting this pin "Low" configures Channel (n) to output the recovered data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of RxClk_(n).
CLOCK INTERFACE
PIN # 47 99 103 NAME EXClk_0 EXClk_1 EXClk_2 TYPE I DESCRIPTION External Reference Clock Input - Channel (n): Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz clock signal for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 applications. The Channel (n) Clock Recovery PLL uses this signal as a Reference Signal for Declaring and Clearing the Receive Loss of Lock Alarm. The Clock recovery PLL also generates the exact clock for the LIU. It is permissible to use the same clock that drives the TxClk_(n) input pin. It is permissible to operate the three Channels at different data rates.
OPERATING MODE SELECT
PIN # 93 NAME SR/(DR) TYPE I DESCRIPTION Receive Output Single-Rail/Dual-Rail Select: Setting this pin "High" configures the Receive Sections of all Channels to output data in a Single-Rail Mode to the Terminal Equipment. Setting this pin "Low" configures the Receive Section of all Channels to output data in a Dual-Rail Mode to the Terminal Equipment.
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XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
OPERATING MODE SELECT
PIN # 64 NAME SDO/(E3_0) TYPE I/O DESCRIPTION Serial Data Output from the Microprocessor Serial Interface/ E3_Mode Select - Channel 0: The function of this pin depends on whether the XRT73L03A is operating in the HOST Mode or in the Hardware Mode. HOST Mode Operation - Serial Data Output for the Microprocessor Serial Interface: This pin serially outputs the contents of the specified Command Register during Read Operations. The data is updated on the falling edge of the SClk input signal and tri-stated upon completion of data transfer. Hardware Mode Operation - E3 Mode Select - Channel 0: This input pin is used to configure Channel 0 in the XRT73L03A to operate in the E3 or STS/DS3 Modes. Setting this input pin to "High" configures Channel 0 to operate in the E3 Mode. Setting this input pin to "Low" configures Channel 0 to operate in either the DS3 or STS-1 Modes, depending upon the state of the STS-1/DS3_0 input pin.
NOTE: This pin is internally pulled "Low" when XRT73L03A is in the Hardware Mode.
92 102 E3_1 E3_2 I E3 Select Input - Channel (n): A "High" on this pin configures Channel (n) of the XRT73L03A to operate in the E3 Mode. A "Low" on this pin configures Channel (n) of the XRT73L03A to check the state of the STS-1/DS3_(n) input pin
NOTE: This input pin is ignored and should be connected to GND if the XRT73L03A is operating in the HOST Mode.
65 95 101 STS-1/DS3_0 STS-1/DS3_1 STS-1/DS3_2 I STS-1/DS3 Select Input - Channel (n): "High" for STS-1 and "Low" for DS3 Operation. The XRT73L03A ignores this pin if the E3_(n) pin is set to "1". This input pin is ignored if the XRT73L03A is operating in the HOST Mode. NOTE: This pin should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode, (internally pulled-down). HOST/Hardware Mode Select: This input pin is used to enable or disable the Microprocessor Serial Interface (e.g., consisting of the SDI, SDO, SClk, and CS pins). Setting this input pin "High" enables the Microprocessor Serial Interface (e.g. configures the XRT73L03A to operate in the HOST Mode). In this mode, configure the XRT73L03A via the Microprocessor Serial Interface. When the XRT73L03A is operating in the HOST Mode, then it ignores the states of many of the discrete input pins. Setting this input pin "Low" disables the Microprocessor Serial Interface (e.g., configures the XRT73L03A to operate in the Hardware Mode). In this mode, many of the external input control pins are functional.
42
HOST/(HW)
I
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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
CONTROL AND ALARM INTERFACE
PIN # 31 4 15 NAME MRing_0 MRing_1 MRing_2 TYPE I DESCRIPTION
Monitor Ring Input - Channel (n):
The bipolar line output signal from TRing_(n) can be connected to this pin via a 270-ohm resistor in order to check for line driver failure. This pin is internally pulled "High".
30 5 16
MTIP_0 MTIP_1 MTIP_2
I
Monitor Tip Input - Channel (n):
The bipolar line output signal from TTIP_(n) can be connected to this pin via a 270-ohm resistor in order to check for line driver failure. This pin is internally pulled "High".
38 120 21 36 6 7
DMO_0 DMO_1 DMO_2 TAOS_0 TAOS_1 TAOS_2
O
Drive Monitor Output - Channel (n): If no transmitted AMI signal is present on MTIP_(n) and MRing_(n) input pins for 12832 TxClk periods, then DMO_(n) toggles and remains "High" until the next AMI signal is detected. Transmit All Ones Select - Channel (n): A "High" on this pin causes the Transmit Section, within Channel (n), to generate and transmit a continuous AMI all "1's" pattern onto the line. The frequency of this "1's" pattern is determined by TxClk_(n). This input pin is ignored if the XRT73L03A is operating in the HOST Mode. NOTE: This pin should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode, (internally pulled-down).
I
55 107 58
RLOS_0 RLOS_1 RLOS_2
O
Receive Loss of Signal Output Indicator - Channel (n):
This output pin toggles "High" if Channel (n) has detected a Loss of Signal Condition in the incoming line signal. The criteria that the XRT73L03A uses to declare an LOS Condition depends upon whether the device is operating in the E3 or STS-1/DS3 Mode.
57 105 60
RLOL_0 RLOL_1 RLOL_2
O
Receive Loss of Lock Output Indicator - Channel (n):
This output pin toggles "High" if Channel (n) has detected a Loss of Lock Condition. Channel (n) declares an LOL (Loss of Lock) Condition if the recovered clock frequency deviates from the Reference Clock frequency (available at the EXClk(n) input pin) by more than 0.5%.
56 106 59
LCV_0 LCV_1 LCV_2
O
Line Code Violation Indicator - Channel 0: Whenever the Receive Section of Channel (n) detects a Line Code Violation, it pulses this output pin "High". This output pin remains "Low" at all other times. NOTE: The XRT73L03A outputs an NRZ pulse via this output pin. It is advisable to sample this output pin via the RxClk_(n) clock output signal.
66
ICT
I
In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a high-impedance state to allow for in-circuit testing. This pin should be set to "High" for normal operation. This pin is internally pulled "High".
67 89 75
LOSTHR_0 LOSTHR_1 LOSTHR_2
I
Loss of Signal Threshold Control - Channel (n):
Forcing the LOSTHR_(n) pin to GND or VDD provides two settings. This pin must be set to a "High" or "Low" level upon power up and should not be changed during operation. This pin is only applicable during DS3 or STS-1 operations.
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REV. 2.0.4
CONTROL AND ALARM INTERFACE
PIN # 68 88 76 NAME LLB_0 LLB_1 LLB_2 TYPE I DESCRIPTION
Local Loop-back - Channel (n):
This input pin along with RLB_(n) dictates which Loop-Back mode Channel (n) is operating in. A "High" on this pin with RLB_(n) set to "Low" configures Channel (n) to operate in the Analog Local Loop-Back Mode. A "High" on this pin with RLB_(n) also being set to "High" configures Channel (n) to operate in the Digital Local Loop-Back Mode. NOTE: This pin is ignored and should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode.
69 87 77
RLB_0 RLB_1 RLB_2
I
Remote Loop-Back - Channel (n):
This input pin in conjunction with LLB_(n) dictates which Loop-Back mode Channel (n) is operating in. A "High" on this pin with LLB_(n) being set to "Low" configures Channel (n) to operate in the Remote Loop-Back Mode. A "High" on this pin with LLB_(n) also being set to "High" configures Channel (n) to operate in the Digital Local Loop-Back Mode. NOTE: This pin is ignored and should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode.
112
LOSMUTEN
I
MUTE-upon-LOS Enable Input (Hardware Mode): This input pin is use to configure the XRT73L03A, while it is operating in the Hardware Mode, to Mute the recovered data via the RPOS_(n), RNEG_(n) output pins whenever one of the Channels declares an LOS conditions. Setting this input pin "High" configures all Channels to automatically pull the RPOS_(n) and RNEG_(n) output pins "Low" whenever it is declaring an LOS condition, thereby Muting the data being output to the Terminal Equipment. Setting this input pin "Low" configures all Channels to NOT automatically Mute the recovered data whenever an LOS condition is declared. NOTES: This pin is ignored and should be tied to GND if the XRT73L03A is going to be operating in the HOST Mode. This pin is internally pulled "Low".
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3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
MICROPROCESSOR INTERFACE
PIN # 61 NAME CS/ (ENDECDIS) TYPE I DESCRIPTION Microprocessor Serial Interface - Chip Select Input/EncoderDecoder Disable Input: This pin's functionality depends on whether the XRT73L03A is operating in the HOST or Hardware Mode. HOST Mode - Chip Select Input The Local Microprocessor must assert this pin (set it to "0") in order to enable communication with the XRT73L03A via the Microprocessor Serial Interface.
NOTE: This pin is internally pulled "High".
Hardware Mode - Encoder/Decoder Disable Input Setting this input pin "High" disables the B3ZS/HDB3 Encoder & Decoder blocks in the XRT73L03A and configures it to transmit and receive the line signal in an AMI format. Setting this input pin "Low" enables the B3ZS/HDB3 Encoder & Decoder blocks and configures it to ransmit and receive the line signal in the B3ZS format for STS-1/DS3 operation or in the HDB3 format for E3 operation.
NOTE: If the XRT73L03A is operating in the Hardware Mode, this pin setting configures the B3ZS/HDB3 Encoder and Decoder Blocks for all Channels.
63 SDI/(RxOFF_0) I Serial Data Input for the Microprocessor Serial Interface/Receiver Shut OFF Input - Channel 0: The function of this input pin depends on whether the XRT73L03A is operating in the HOST Mode or in the Hardware Mode. HOST Mode - Serial Data Input for the Microprocessor Serial Interface: To read or write data into the Command Registers over the Microprocessor Serial Interface, apply the Read/Write bit, the Address Values of the Command Registers and Data Value to be written during Write Operations to this pin. This input is sampled on the rising edge of the SClk pin. Hardware Mode - Channel 0 Receiver Shut OFF Input: Setting this input pin "High" shuts off the Channel 0 receiver. Setting this input pin "Low" enables the Receive Section for full operation. 62 SClk/(RxOFF_1) I Microprocessor Serial Interface Clock Signal/Receiver Shut OFF Input - Channel 1: The function of this pin depends on whether the XRT73L03A is operating in the HOST Mode or in the Hardware Mode. HOST Mode - Microprocessor Serial Interface Clock Signal: This signal is used to sample the data on the SDI pin on the rising edge of this signal. Additionally, during Read operations the Microprocessor Serial Interface updates the SDO output on the falling edge of this signal. Hardware Mode - Receiver Shut OFF input - Channel 1: Setting this input pin "High" shuts off the Channel 1 receiver. Setting this input pin "Low" enables the Receive Section for full operation.
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MICROPROCESSOR INTERFACE
PIN # 104 NAME RxOFF_2 TYPE I DESCRIPTION Receiver Shut OFF Input - Channel 2: Hardware Mode - Receiver Shut OFF Input - Channel 2: Setting this input pin "High" shuts off the Receive Section in Channel 2. Setting this input pin "Low" enables the Receive Section for full operation. 96 REGR/ RxClkINV I Register Reset Input pin (Invert RxClk(n)) Output - Select): The function of this pin depends upon whether the XRT73L03A is operating in the HOST Mode or in the Hardware Mode.
NOTE: This pin is internally pulled "High".
In the HOST-Mode - Register Reset Input: Setting this input pin "Low" causes the XRT73L03A to reset the contents of the Command Registers to their default settings and default operating configuration. In the Hardware Mode - Invert RxClk Output Select: Setting this input pin "High" configures the Receive Section of all Channels in the XRT73L03A to invert their RxClk_(n) clock output signals and configures Channel (n) to output the recovered data via the RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n). Setting this pin "Low" configures Channel (n) to output the recovered data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of RxClk_(n).
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REV. 2.0.4
POWER AND GROUND PINS
PIN # 11 13 14 17 19 22 26 28 37 39 40 41 46 48 54 70 73 78 81 83 86 94 97 98 108 113 114 118 119 NAME TxAVDD_1 TxAGND_1 TxAGND_2 TxAGND_2 TxAVDD_2 TxAVDD_2 TxAGND_0 TxAVDD_0 TxAVDD_0 TxAGND_0 AGND_0 RxDVDD_2 RxDGND_2 RxDVDD_0 RxDGND_0 RxAVDD_0 RxAGND_0 RxAVDD_2 RxAGND_2 RxAGND_1 RxAVDD_1 AGND_2 EXDGND EXDVDD RxDGND_1 RxDVDD_1 AGND_1 TxAGND_1 TxAVDD_1 TYPE **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** DESCRIPTION Transmitter Analog Supply, 3.3V + 5% - Channel(n) Transmitter Analog Ground - Channel(n) Transmitter Analog Ground - Channel(n) Transmitter Analog Ground - Channel(n) Transmitter Analog Supply, 3.3V + 5% - Channel(n) Transmitter Analog Supply, 3.3V + 5% - Channel(n) Transmitter Analog Ground - Channel(n) Transmitter Analog Supply, 3.3V + 5% - Channel(n) Transmitter Analog Supply, 3.3V + 5% - Channel(n) Transmitter Analog Ground - Channel (n) Analog Ground - Channel (n) Receiver Digital Supply 3.3V + 5% Channel (n) Receiver Digital Ground - Channel(n) Receiver Digital Supply 3.3V + 5% Channel (n) Receiver Digital Ground - Channel(n) Receiver Analog Supply 3.3V + 5% Channel (n) Reciever Analog Ground Channel (n) Receiver Analog Supply 3.3V + 5% - Channel (n) Receiver Analog Ground - Channel (n) Receiver Analog Ground - Channel (n) Receiver Analog Supply 3.3V + 5% - Channel (n) Analog Ground - Channel (n) External Reference Clock Ground External Reference Clock Power Supply Receiver Digital Ground - Channel(n) Receiver Digital Supply 3.3V + 5% Channel (n) Analog Ground - Channel (n) Transmitter Analog Ground - Channel(n) Transmitter Analog Supply, 3.3V + 5% - Channel(n)
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XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
NO CONNECTION PINS
PIN # 52 53 90 91 NAME NC NC NC NC TYPE No connection No connection No connection No connection DESCRIPTION
14
XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Operating Temperature Supply Voltage Range Theta-JA Theta-JC - 65C to + 150C - 40C to + 85C -0.5V to +3.465V 23 C/W 7 C/W
NOTE: The XRT73L03A is assembled in a thermally enhanced package with an integral Copper Heat Slug. The Heat Slug is solder plated and is exposed on the bottom of the package and is electrically connected to the internal GND connections of the device. This Heat Slug can be sol-
dered to the mounting board if desired, but must be electrically isolated from any VDD connections.
ELECTRICAL CHARACTERISTICS (TA = 25C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL PARAMETER MIN.
TYP.
MAX.
UNITS
DC Electrical Characteristics
DVDD AVDD ICC VIL VIH VOL VOH IL Digital DC Supply Voltage Analog DC Supply Voltage Supply Current (Measured while Transmitting and Receiving all "1's") Input Low Voltage * Input High Voltage * Output Low Voltage, IOUT = -4.0mA * Output High Voltage, IOUT = 4.0mA * Input Leakage Current * 2.8 10 2.0 3.135 3.135 3.3 3.3 3.465 3.465 515 0.8 5.0 0.4 V V mA V V V V A
NOTE: * Not applicable to pins with pull-down resistors.
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XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) AC ELECTRICAL CHARACTERISTICS (SEE FIGURE 5) TERMINAL SIDE TIMING PARAMETERS (SEE FIGURE 6 AND FIGURE 7) -- {(n) = 0, 1 OR 2 }
SYMBOL PARAMETER TxClk_(n) Clock Duty Cycle (STS-1/DS3) TxClk_(n) Clock Duty Cycle (E3) TxClk_(n) Frequency (SONET STS-1) TxClk_(n) Frequency (DS3) TxClk_(n) Frequency (E3) tRTX tFTX tTSU tTHO tLCVO tTDY TxClk_(n) Clock Rise Time (10% to 90%) TxClk_(n) Clock Fall Time (90% to 10%) TPData_(n)/TNData_(n) to TxClk_(n) Falling Set up time TPData_(n)/TNData_(n) to TxClk_(n) Falling Hold time RxClk_(n) to rising edge of LCV_(n) output delay TTIP_(n)/TRing_(n) to TxClk_(n) Rising Propagation Delay time RxClk_(n) Clock Duty Cycle RxClk_(n) Frequency (SONET STS-1) RxClk_(n) Frequency (DS3) RxClk_(n) Frequency (E3) tCO tRRX tFRX CI CL RxClk_(n) to RPOS_(n)/RNEG_(n) Delay Time RxClk_(n) Clock Rise Time (10% to 90%) RxClk_(n) Clock Fall Time (10% to 90%) Input Capacitance Load Capacitance 0 3 3 MIN. 30 30
TYP.
MAX. 70 70
UNITS % % MHz MHz MHz
50 50 51.84 44.736 34.368 3 3 1.5 1.5 2.5 8 50 51.84 44.736 34.368 2.5 1.5 1.5
5 5
ns ns ns ns ns ns % MHz MHz MHz ns ns ns
10 10
pF pF
NOTES: 1. All XRT73L03A digital inputs are designed to be TTL 5V compliant.
2. All XRT73L03A digital outputs are also TTL 5V compliant. However, these outputs will not drive to 5V nor will they accept external 5V pull-ups.
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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
FIGURE 5. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES (TYPICAL CHANNEL)
TTIP_(n) Channel (n) Channel (n) R1 31.6
TxPOS_(n) TxNEG_(n) TxLineClk_(n)
TPData_(n) TNData_(n) TxClk_(n)
1:1 R2 31.6 TRing_(n) Only One Channel Shown
R3 75
FIGURE 6. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE
tRTX TClk tTSU TPDATA or TNDATA TTIP or TRING tTDY tTHO tFTX
FIGURE 7. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE
tRRX RClk tLCVO LCV tCO RPOS or RNEG tFRX
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XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS E3 APPLICATION TRANSMIT CHARACTERISTICS (SEE FIGURE 5)
SYMBOL PARAMETER Transmit Output Pulse Amplitude (Measured at Secondary Output of Transformer) Transmit Output Pulse Amplitude Ratio Transmit Output Pulse Width Transmit Output Pulse Width Ratio Transmit Output Jitter with jitter-free input @ TxClk_(n) Receive Line Characteristics Receive Sensitivity (Length of cable) Interference Margin Signal Level to Declare Loss of Signal Signal Level to Clear Loss of Signal Occurrence of LOS to LOS Declaration Time Termination of LOS to LOS Clearance Time Intrinsic Jitter (all "1's" pattern) Jitter Tolerance @ Jitter Frequency = 100Hz Jitter Tolerance @ Jitter Frequency = 1kHz Jitter Tolerance @ Jitter Frequency = 10kHz Jitter Tolerance @ Jitter Frequency = 800kHz 64 30 4 0.15 0.20 -15 10 10 0.02 255 255 1200 -20 1400 -15 -35 feet dB dB dB UI UI UI UI UI UI UI MIN. 0.9 0.95 12.5 0.95 TYP. 1.0 1.00 14.55 1.00 0.02 MAX 1.1 1.05 16.5 1.05 0.05 UIpp ns UNITS Vpk
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3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS SONET STS-1 APPLICATION TRANSMIT CHARACTERISTICS (SEE FIGURE 5)
SYMBOL PARAMETER Transmit Output Pulse Amplitude (Measured with TxLEV=0) Transmit Output Pulse Amplitude (Measured with TxLEV=1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Transmit Output Jitter with jitter-free input @ TxClk_(n) Receive Line Characteristics Receive Sensitivity (Length of Cable) Signal Level to Declare or Clear Loss of Signal (see Table 5 ) Intrinsic Jitter (all "1's" pattern) Jitter Tolerance @ Jitter Frequency = 100Hz Jitter Tolerance @ Jitter Frequency = 1kHz Jitter Tolerance @ Jitter Frequency = 10kHz Jitter Tolerance @ Jitter Frequency = 400kHz 64 64 5 0.15 0.35 0.02 900 1100 feet mV UI UI UI UI UI MIN. 0.65 0.93 8.6 0.9 TYP. 0.75 0.98 9.65 1.0 0.02 MAX 0.90 1.08 10.6 1.1 0.05 UI UNITS Vpk Vpk ns
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XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS DS3 APPLICATION TRANSMIT CHARACTERISTICS (SEE FIGURE 5)
SYMBOL PARAMETER Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=0) Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Transmit Output Jitter with jitter-free input @ TxClk_(n) Receive Line Characteristics Receive Sensitivity (Length of cable) Signal Level to Declare or Clear Loss of Signal (see Table 5 ) Intrinsic Jitter (all "1's" pattern) Jitter Tolerance @ Jitter Frequency = 100Hz Jitter Tolerance @ Jitter Frequency = 1kHz Jitter Tolerance @ Jitter Frequency = 10kHz Jitter Tolerance @ Jitter Frequency = 300kHz (Cat II) 64 64 5 0.35 0.45 900 1100 70 0.02 feet mV UI UI UI UI UI MIN. 0.65 0.9 10.10 0.9 TYP. 0.75 1.0 11.18 1.0 0.02 MAX 0.85 1.1 12.28 1.1 0.05 UI UNITS Vpk Vpk ns
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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
Figure 8, Figure 9 and Figure 10 present the Pulse Template requirements for the E3, DS3 and STS-1 Rates. FIGURE 8. ITU-T G.703 TRANSMIT OUTPUT PULSE TEMPLATE FOR E3 APPLICATIONS
17 ns (14.55 + 2.45)
V = 100%
8.65 ns
Nominal Pulse
50%
14.55ns 12.1ns (14.55 - 2.45) 10% 20%
10% 0%
FIGURE 9. BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS
DS3 Pulse Template
1.2
1
0.8 Normalized Amplitude
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
-1
0
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
1
1
2
3 1.
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
0.
0.
0.
0.
0.
0.
0.
0.
0.
1.
1.
Time, in UI
21
1.
4
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
FIGURE 10. BELLCORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
STS-1 Pulse Template
1.2
1
0.8 Normalized Amplitude
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
-0 .7
-0 .9
-0 .8
-0 .6
-0 .5
-0 .4
-0 .3
-0 .2
-0 .1
0. 1
0. 2
0. 3
0. 4
0
0. 5
Time, in UI
FIGURE 11. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS SClk SDI SDO
1
2
3
4
5
6
7
8
9
0. 6
0. 7
10
0. 8
11
0. 9
12
1. 1
13
1. 2
14
1. 3
1. 4
-1
1
15
16
R/W
A0
A1
A2
A3
A4
0
A6
D0
D1
D2
D3
D4
D5
D6
D7
High Z
D0 D1 D2 D3 D4 0 0 0
High Z
NOTES: 1. A5 is always "0". 2. R/W = "1" for "Read" Operations
3. R/W = "0" for "Write" Operations 4. A shaded pulse, denotes a "don't care" value.
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3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE 12)
SYMBOL t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 PARAMETER CS Low to Rising Edge of SClk Setup Time CS High to Rising Edge of SClk Hold Time SDI to Rising Edge of SClk Setup Time SDI to Rising Edge of SClk Hold Time SClk "Low" Time SClk "High" Time SClk Period CS Low to Rising Edge of SClk Hold Time CS "Inactive" Time Falling Edge of SClk to SDO Valid Time Falling Edge of SClk to SDO Invalid Time Rising edge of CS to High Z Rise/Fall time of SDO Output 100 20 MIN. 5 5 5 5 65 65 160 5 160 80 65 80 80 TYP. MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTE: The load is 10pF
FIGURE 12. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29 CS t22 SCLK t23 SDI t24 R/W A0 A1 t25 t21 t27 t26 t28
CS
SCLK t30 SDO Hi-Z D0 t31 D1 Hi-Z t33 D2 D7 t32
SDI
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XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
SYSTEM DESCRIPTION
A functional block diagram of the XRT73L03A E3/ DS3/STS-1 Transceiver IC is presented in Figure 13. The XRT73L03A contains three separate channels with three distinct sections: * The Transmit Section - Channels 0, 1 and 2 * The Receive Section - Channels 0, 1 and 2 * The Microprocessor Serial Interface Section THE TRANSMIT SECTION - CHANNELS 0, 1 AND 2 The Transmit Section, within each Channel, accepts TTL/CMOS level signals from the Terminal Equipment in either a Single-Rail or Dual-Rail format. The Transmit Section then takes this data and does the following: * Encode this data into the B3ZS format if the DS3 or SONET STS-1 Modes has been selected or into the HDB3 format if the E3 Mode has been selected. * Convert the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the various industry standard pulse template requirements. * Drive these pulses onto the line via the TTIP_(n) and TRing_(n) output pins across a 1:1 Transformer.
NOTE: The Transmit Section drives a "1" (or a Mark) onto the line by driving either a positive or negative polarity pulse across the 1:1 Transformer within a given bit period. The Transmit Section drives a "0" (or a Space) onto the line by driving no pulse onto the line.
1. The Microprocessor Serial Interface block is disabled. 2. The XRT73L03A is configured via input pin settings. The XRT73L03A can be configured to operate in the Hardware Mode by tying the HOST/(HW) input pin to GND. Each of the pins associated with the Microprocessor Serial Interface takes on their alternative role as defined inTable 1. TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73L03A IS OPERATING IN THE HARDWARE MODE
PIN # 61 62 63 64 96 PIN NAME CS/(ENDECDIS) SClk/(RxOFF_1) SDI/(RxOFF_0) SDO/(E3_0) REGR/(RxClkINV) FUNCTION, WHILE IN
HARDWARE MODE
ENDECDIS RxOFF_1 RxOFF_0 E3_0 RxClkINV
When the XRT73L03A is operating in the Hardware Mode, all of the remaining input pins become active. b. Operating in the HOST Mode The XRT73L03A can be configured to operate in the HOST Mode by tying the HOST/(HW) input pin to VDD. When the XRT73L03A is operating in the HOST Mode, then the following is true. 1. The Microprocessor Serial Interface block is enabled. Writing the appropriate data into the on-chip Command Registers makes many configuration selections. 2. All of the following input pins are disabled and should be connected to ground: * Pins 8, 9 & 35 - TxLEV_(n) * Pins 6, 7 & 36 - TAOS_(n) * Pin 74, 82 & 100 - REQEN_(n) * Pin 69, 77 & 87 - RLB_(n) * Pin 68, 76 & 88 - LLB_(n) * Pin 92 & 102 - E3_(n) * Pin 65, 95 & 101 - STS1/DS3_(n) In HOST Mode Operation, the TxOFF_(n) input pins can be used to turn on or turn off the Transmit Output Drivers within all Channels concurrently. The intent behind this feature is to permit a system designed for
THE RECEIVE SECTION - CHANNELS 0, 1 AND 2 The Receive Section, within each Channel, receives a bipolar signal from the line via the RTIP and RRing signals through a 1:1 Transformer or 0.01F Capacitor. The recovered clock and data outputs to the Local Terminal Equipment in the form of CMOS level signals via the RPOS_(n), RNEG_(n) and RxClk_(n) output pins. THE MICROPROCESSOR SERIAL INTERFACE The XRT73L03A can be configured to operate in either the Hardware Mode or the HOST Mode. The XRT73L03A contains three identical channels. The Microprocessor Interface Inputs are common to all channels. The descriptions that follow refer to Channel(n) where (n) represents channel 0, 1 or 2. a. Operating in the Hardware Mode When the XRT73L03A is operating in the Hardware Mode, then the following is true:
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REV. 2.0.4
redundancy to quickly switch out a defective line card and switch-in the back-up line card. FIGURE 13. FUNCTIONAL BLOCK DIAGRAM OF THE XRT73L03A
E3_(n) STS-1/DS3_(n) Host/(HW) RLOL_(n) EXClk_(n) RxOFF RxClkINV
RTIP_(n) RRing_(n) REQEN_(n)
AGC/ Equalizer Peak Detector
Slicer
Clock Recovery Data Recovery
Invert
RxClk_(n)
LOSTHR_(n) SDI SDO SClk CS REGR Serial Processor Interface
LOS Detector
HDB3/ B3ZS Decoder
RPOS_(n) RNEG_(n) LCV_(n) ENDECDIS RLOS_(n) LLB_(n) RLB_(n) TAOS_(n)
Loop MUX
TTIP_(n) Pulse Shaping TRing_(n) MTIP_(n) MRing_(n) DMO_(n) Tx Control
HDB3/ B3ZS Encoder
Transmit Logic Duty Cycle Adjust
TPData_(n) TNData_(n) TxClk_(n) TxLEV_(n) TxOFF_(n)
Device Monitor
Channel 0 - (n) = 0 Channel 1 - (n) = 1 Channel 2 - (n) = 2
Notes: 1. (n) = 0, 1, or 2 for respective Channels 2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
1.0 SELECTING THE DATA RATE Each channel within the XRT73L03A can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. Further, each channel can be configured to operate in a mode/data rate that is independent of the other channels. Two methods are available to select the data rate for each channel of the XRT73L03A.
1.1 CONFIGURING CHANNEL(n) For the following disscussion the reader should refer toTable 2 to determine the appropriate Address for each command register of each channel in the XRT73L03A. The command register description refers to CR(x)-(n), where (x) = 0 to 7 and (n) refers to a particular channel of the XRT73L03A.
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XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
TABLE 2: HEXADECIMAL ADDRESSES AND BIT FORMATS OF XRT73L03A COMMAND REGISTERS
REGISTER BIT-FORMAT ADDRESS COMMAND REGISTER TYPE D4 CHANNEL0 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 CR0-0 CR1-0 CR2-0 CR3-0 CR4-0 CR5-0 CR6-0 CR7-0 RO R/W R/W R/W R/W R/W R/W R/W RLOL_0 TxOFF_0 Reserved SR/(DR)_0 Reserved Reserved Reserved Reserved RLOS_0 TAOS_0 ENDECDIS_0 LOSMUT_0 STS-1/DS3_0 Reserved Reserved Reserved ALOS_0 TxClkINV_0 ALOSDIS_0 RxOFF_0 E3_0 Reserved Reserved Reserved DLOS_0 TxLEV_0 DLOSDIS_0 RxClk_0INV LLB_0 Reserved Reserved Reserved DMO_0 TxBIN_0 REQEN_0 Reserved RLB_0 Reserved Reserved Reserved D3 D2 D1 D0
CHANNEL1 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F CR0-1 CR1-1 CR2-1 CR3-1 CR4-1 CR5-1 CR6-1 CR7-1 RO R/W R/W R/W R/W R/W R/W R/W RLOL_1 TxOFF_1 Reserved SR/(DR)_1 Reserved Reserved Reserved Reserved RLOS_1 TAOS_1 ENDECDIS_1 LOSMUT_1 STS-1/DS3_1 Reserved Reserved Reserved ALOS_1 TxClkINV_1 ALOSDIS_1 RxOFF_1 E3_1 Reserved Reserved Reserved DLOS_1 TxLEV_1 DLOSDIS_1 RxClk_1INV LLB_1 Reserved Reserved Reserved DMO_1 TxBIN_1 REQEN_1 Reserved RLB_1 Reserved Reserved Reserved
CHANNEL2 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 CR0-2 CR1-2 CR2-2 CR3-2 CR4-2 CR5-2 CR6-2 CR7-2 RO R/W R/W R/W R/W R/W R/W R/W RLOL_2 TxOFF_2 Reserved SR/(DR)_2 Reserved Reserved Reserved Reserved RLOS_2 TAOS_2 ENDECDIS_2 LOSMUT_2 STS-1/DS3_2 Reserved Reserved Reserved ALOS_2 TxClkINV_2 ALOSDIS_2 RxOFF_2 E3_2 Reserved Reserved Reserved DLOS_2 TxLEV_2 DLOSDIS_2 RxClk_2INV LLB_2 Reserved Reserved Reserved DMO_2 TxBIN_2 REQEN_2 Reserved RLB_2 Reserved Reserved Reserved
Address: The register addresses are presented in the Hexadecimal format.
Type: The Command Registers are either Read-Only (RO) type of registers or Read/Write (R/W) type of registers.
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REV. 2.0.4
The default value for each of the bit-fields within these registers is "0".
DS3_(n) input pins (where n = 0, 1 or 2) to the appropriate logic states, as presented below inTable 3.
a. Operating in the Hardware Mode. In order to configure individual Channels into the appropriate mode, set the E3_(n), and the STS-1/ TABLE 3: SELECTING THE DATA RATE FOR CHANNEL(n) VIA THE E3_(n) AND STS-1/DS3_(n) INPUT PINS (HARDWARE MODE)
DATA RATE E3 (34.368 Mbps) DS3 (44.736 Mbps) STS-1 (51.84 Mbps) STATE OF E3_(n) PIN 1 0 0 STATE OF STS-1/DS3_(n) PIN X (Don't Care) 0 1 MODE OF B3ZS/HDB3 ENCODER/ DECODER BLOCKS HDB3 B3ZS B3ZS
b. Operating in the HOST Mode. To configure a Channel into the appropriate mode, write the appropriate values into the STS-1/DS3_(n) and E3_(n) bit-fields within the Command Register CR4-(n), as illustrated below (refer to Table 2 for the correct address for each channel). COMMAND REGISTER, CR4-(n)
D4 X x D3 STS-1/(DS3)_(n)) x D2 E3_(n) x D1 D0
* TxClk_(n) Duty Cycle Adjust Block * HDB3/(B3ZS) Encoder * Pulse Shaping Block The purpose of the Transmit Section is to take TTL/ CMOS level data from the terminal equipment and encode it into a format such that it can: 1. Be efficiently transmitted over coaxial cable at E3, DS3, or STS-1 data rates. 2. Be reliably received by the Remote Terminal Equipment at the other end of the E3, DS3, or STS-1 data link. 3. Comply with the applicable pulse template requirements. 2.1 THE TRANSMIT LOGIC BLOCK The purpose of the Transmit Logic Block is to accept either Dual-Rail or Single-Rail (e.g., a binary data stream) TTL/CMOS level data and timing information from the Terminal Equipment. 2.1.1 Accepting Dual-Rail Data from the Terminal Equipment Whenever the XRT73L03A accepts Dual-Rail data from the Terminal Equipment, it does so via the following input signals: * TPData_(n) * TNData_(n) * TxClk_(n) Figure 14 illustrates the typical interface for the transmission of data in a Dual-Rail Format between the Terminal Equipment and the Transmit Section of the XRT73L03A.
LLB_(n) RLB_(n) x x
Table 4 relates the values of these two bit-fields to the selected data rates. TABLE 4: SELECTING THE DATA RATE FOR CHANNEL(n) VIA THE STS-1/DS3_(n) AND THE E3_(n) BIT-FIELDS WITHIN THE APPROPRIATE COMMAND REGISTER (HOST MODE)
SELECTED DATA RATE E3 DS3 STS-1 STS-1/DS3_(n) (D3) X (Don't Care) 0 1 E3_(n) (D2) 1 0 0
2.0 THE TRANSMIT SECTION Figure 13 indicates that the Transmit Section within each Channel of the XRT73L03A consists of the following blocks: * Transmit Logic Block
27
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
FIGURE 14. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE TRANSMITTING TERMINAL EQUIPMENT TO THE TRANSMIT SECTION OF A CHANNEL
TxPOS Terminal Equipment (E3/DS3 or STS-1 Framer) TxNEG TxLineClk
TPData TNData TxClk
Transmit Logic Block
Exar E3/DS3/STS-1 LIU
The manner that the LIU handles Dual-Rail data is described below and illustrated in Figure 15. The Transmit Section (of a Channel) typically samples the
data on the TPData_(n) and TNData_(n) input pins on the falling edge of TxClk_(n).
FIGURE 15. THE XRT73L03A SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS
Data
1
1
0
TPData TNData TxClk
TxClk_(n) is the clock signal that is of the selected data rate frequency, E3 = 34.368 MHz, DS3 = 44.736 MHz and STS-1 = 51.84 MHz. If the Transmit Section samples a "1" on the TPData_(n) input pin, then the Transmit Section of the device ultimately generates a positive polarity pulse via the TTIP_(n) and TRing_(n) output pins across a 1:1 transformer. If the Transmit Section samples a "1" on the TNData_(n) input pin, then the Transmit Section of the device ultimately generates a negative polarity pulse via the TTIP_(n) and TRing_(n) output pins across a 1:1 transformer. 2.1.2 Accepting Single-Rail Data from the Terminal Equipment To transmit data in a Single-Rail data from the Terminal Equipment, configure the XRT73L03A in the HOST Mode. Write a "1" into the TxBin_(n) (TRANSMIT BINary) bit-field of Command Register CR1-(n) shown below. 28
NOTE: Please refer to Table 2 for the Address of the individual Channel(n).
COMMAND REGISTER CR1-(n)
D4 D3 D2 D1 D0
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBin_(n)
X
X
X
X
1
The Transmit Section of each channel samples this input pin on the falling edge of the TxClk_(n) clock signal and encodes this data into the appropriate bipolar line signal across the TTIP_(n) and TRing_(n) output pins.
NOTES: 1. In this mode, the Transmit Logic Block ignores the TNData_(n) input pin.
XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
2. If the Transmit Section of a given channel is configured to accept Single-Rail data from the Terminal Equipment, the B3ZS/HDB3 Encoder must be enabled.
Figure 16 illustrates the behavior of the TPData_(n) and TxClk_(n) signals when the Transmit Logic Block has been configured to accept Single-Rail data from the Terminal Equipment.
FIGURE 16. THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SGNALS, WHILE THE TRANSMIT LOGIC BLOCK IS ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
Data
1
1
0
TPData TxClk
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY
number of consecutive zeros that can exist within the line signal. 2.3.1 B3ZS Encoding If the XRT73L03A has been configured to operate in the DS3 or SONET STS-1 Modes, then the HDB3/ B3ZS Encoder blocks operate in the B3ZS Mode. When the Encoder is operating in this mode, it parses through and searches the Transmit Binary Data Stream from the Transmit Logic Block for the occurrence of three (3) consecutive zeros (e.g., "000"). If the B3ZS Encoder finds an occurrence of three consecutive zeros, then it substitutes these three "0's", with either a "00V" or a "B0V" pattern. Where: "B" represents a Bipolar pulse that is compliant with the Alternating Polarity requirements of the AMI (Alternate Mark Inversion) line code; and "V" represents a Bipolar Violation (e.g., a bipolar pulse that violates the Alternating Polarity requirements of the AMI line code). The B3ZS Encoder decides whether to substitute with either the "00V" or the "B0V" pattern in order to insure that an odd number of bipolar pulses exist between any two consecutive violation pulses. Figure 17 illustrates the B3ZS Encoder at work with two separate strings of three (or more) consecutive zeros
The on-chip Pulse-Shaping circuitry within the Transmit Section of each Channel in the XRT73L03A generates pulses of the appropriate shapes and width to meet the applicable pulse template requirements. The widths of these output pulses are defined by the width of the half-period pulses within the TxClk_(n) signal. However, if the widths of the pulses within the TxClk_(n) clock signal are allowed to vary significantly, this could jeopardize the chip's ability to generate Transmit Output pulses of the appropriate width and thereby not meet the Pulse Template requirement specification. Consequently, the chip's ability to generate compliant pulses could depend upon the duty cycle of the clock signal applied to the TxClk_(n) input pin. The Transmit Clock Duty Cycle Adjust Circuitry accepts clock pulses via the TxClk_(n) input pin at duty cycles ranging from 30% to 70% and converts them to a 50% duty cycle. 2.3 THE HDB3/B3ZS ENCODER BLOCK The purpose of the HDB3/B3ZS Encoder Block is to aid in the Clock Recovery process at the Remote Terminal Equipment by ensuring an upper limit on the
29
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
FIGURE 17. AN EXAMPLE OF B3ZS ENCODING
TClk
TPOS SR data Encoded PDATA Encoded NDATA
1
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0 0
0 0
0 V
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
0
0
0
0
0
Line signal B 0 V
2.3.2 HDB3 Encoding If the XRT73L03A is configured to operate in the E3 Mode, then the HDB3/B3ZS Encoder blocks operate in the HDB3 Mode. When the Encoder is operating in this mode, it parses through and searches the Transmit Data Stream from the Transmit Logic Block for the occurrence of four (4) consecutive zeros (e.g., "0000"). If the HDB3 Encoder finds an occurrence of four consecutive zeros, then it substitutes these four "0's", with either a "000V" or a "B00V" pattern. The FIGURE 18. AN EXAMPLE OF HDB3 ENCODING
TClk
HDB3 Encoder decides whether to substitute with either the "000V" or the "B00V" pattern in order to insure that an odd number of bipolar pulses exist between any two consecutive violation pulses. Figure 18 illustrates the HDB3 Encoder at work with two separate strings of four (or more) consecutive zeros.
TPOS SR data Encoded PDATA Encoded NDATA
1
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0 0
0 0
0 0
0 V
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
Line signal B 0 0 V
2.3.3 Disabling the HDB3/B3ZS Encoder The XRT73L03A HDB3/B3ZS Encoder can be disabled by two methods. a. Operating in the Hardware Mode. The HBD3/B3ZS Encoder blocks of all channels are disabled by setting the ENDECDIS (Encoder/ Decoder Disable) input pin to "1".
NOTE: By executing this step the HDB3/B3ZS Encoder and Decoder blocks in all channels of the XRT73L03A are globally disabled.
a. Operating in the HOST Mode. When the XRT73L03A is operating in the HOST Mode the HDB3/B3ZS Encoders in each channel can be individually enabled or disabled. Disable the HDB3/B3ZS Encoder block in Channel(n) by setting the ENDECDIS(n) bit-field in Command Register (CR2-(n)), to "1"
COMMAND REGISTER CR2-(n)
D4 Reserved D3 ENDECDIS_(n) D2 ALOSDIS_(n) D1 DLOSDIS_(n) D0 REQEN_(n)
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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
COMMAND REGISTER CR2-(n)
D4 X D3 1 D2 X D1 X D0 X
NOTE: This method can only be used if the XRT73L03A is operating in the HOST Mode.
If either of these methods are used to disable the HDB3/B3ZS Encoder, then the LIU transmits the data as received via the TPData_(n) and TNData_(n) input pins. 2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY The Transmit Pulse Shaper Circuitry consists of a Transmit Line Build-Out circuit which can be enabled or disabled by setting the TxLEV_(n) input pin or TxLEV_(n) bit-field to "High"or "Low". The purpose of the Transmit Line Build-Out circuit is to permit config-
uration of each channel to transmit an output pulse which is compliant to either of the following pulse template requirements when measured at the Digital Cross Connect System. Each of these Bellcore specifications state that the cable length between the Transmit Output and the Digital Cross Connect system can range anywhere from 0 to 450 feet. The Isolated DSX-3 Pulse Template Requirement per Bellcore GR-499-CORE is illustrated in Figure 19 and the Isolated STSX-1 Pulse Template Requirement per Bellcore GR-253-CORE is illustrated in Figure 20.
FIGURE 19. THE BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS
D S3 Pu lse T em p late
1.2
1
0.8 Norm a lize d Am plitude
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
-1
0
1
2
3
4
5
6
7
8
9
1
1
2
3 1.
.9
.8
.7
.5
.6
.4
.3
.2
.1
0.
0.
0.
0.
0.
0.
0.
0.
0.
1.
1.
-0
-0
-0
-0
-0
-0
-0
-0
-0
Tim e , in UI
31
1.
4
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
.
FIGURE 20. THE BELLCORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
ST S-1 Pulse T emplate
1.2
1
0.8 Norm a lize d Am plitude
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
0
-1
1
2
3
4
5
8
1
6
7
9
1
2
3 1.
9
8
7
5
6
4
3
2
1
0.
0.
0.
0.
0.
0.
0.
0.
0.
1.
1.
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
Time, in UI
2.4.1 Enabling the Transmit Line Build-Out Circuit If the Transmit Line Build-Out Circuit is enabled, then the Transmit Section of the Channel outputs shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins.
Enable the Transmit Line Build-Out circuit for each channel by doing the following: a. Operating in the Hardware Mode Set the TxLEV_(n) input pin to "Low". b. Operating in the HOST Mode Set the TxLEV_(n) bit-field to "0", as illustrated below.
COMMAND REGISTER, CR1-(n)
D4 TxOFF_(n) 0 D3 TAOS_(n) X D2 TxClkINV_(n) X D1 TxLEV_(n) 0 D0 TxBIN_(n) X
2.4.2 Disabling the Transmit Line Build-Out Circuit If the Transmit Line Build-Out circuit is disabled, then the XRT73L03A outputs partially shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins.
Disable the Transmit Line Build-Out circuit by doing the following: a. Operating in the Hardware Mode Set the TxLEV_(n) input pin to "High". b. Operating in the HOST Mode
32
1.
4
XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
Set the TxLEV_(n) bit-field to "1" as illustrated below. COMMAND REGISTER, CR1-(n)
D4 TxOFF_(n) 0 D3 TAOS_(n) X D2 TxClkINV_(n) X D1 TxLEV_(n) 1 D0 TxBIN_(n) X
2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit The TxLEV_(n) input pins or bit-fields should be set based upon the overall cable length between the Transmitting Terminal and the Digital Cross Connect system where the pulse template measurements are made.
over long cable lengths (e.g., greater than 225 feet) cause these pulses to be properly shaped and comply with the appropriate pulse template requirement.
If the cable length between the Transmitting Terminal and the DSX-3 or STSX-1 is less than 225 feet, enable the Transmit Line Build-Out circuit by setting the TxLEV_(n) input pin or bit-field to "0".
NOTE: In this case, the configured channel outputs shaped (e.g., not square-wave) pulses onto the line via its TTIP_(n) and TRing_(n) output pins. The shape of this output pulse is such that it complies with the pulse template requirements even when subjected to cable loss ranging from 0 to 225 feet.
2.4.4 The Transmit Line Build-Out Circuit and E3 Applications The ITU-T G.703 Pulse Template Requirements for E3 states that the E3 transmit output pulse should be measured at the Secondary Side of the Transmit Output Transformer for Pulse Template compliance. In other words, there is no Digital Cross Connect System pulse template requirement for E3. Consequently, the Transmit Line Build-Out circuit within a given Channel is disabled whenever that channel has been configured to operate in the E3 Mode. 2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73L03A TO THE LINE The E3, DS3 and SONET STS-1 specification documents all state that line signals transmitted over coaxial cable are to be terminated with 75 Ohm resistor. Interface the Transmit Section of the XRT73L03A in the manner illustrated in Figure 21.
If the cable length between the Transmitting Terminal and the DSX-3 or STSX-1 is greater than 225 feet, disable the Transmit Line Build-Out circuit by setting the TxLEV_(n) input pin or bit-field to "1".
NOTE: In this case, the configured channel outputs partially shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. The cable loss that these pulses experience
FIGURE 21. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT73L03A TO THE LINE
TTIP_(n) Channel (n) R1 31.6 J1 BNC
TxPOS_(n) TxNEG_(n) TxLineClk_(n)
TPData_(n) TNData_(n) TxClk_(n)
1:1 R2 31.6 TRing_(n) Only One Channel Shown
33
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
TRANSFORMER RECOMMENDATIONS
PARAMETER Turns Ratio Primary Inductance Isolation Voltage Leakage Inductance VALUE 1:1 40H 1500Vrms 0.6H
PART NUMBER PE-68629 PE-65966 PE-65967 T3001 TG01-0406NS TTI 7601-SM
VENDOR Pulse Pulse Pulse Pulse Halo Trans-Power
INSULATION 3000V 1500V 1500V 1500V 1500V 1500V
PACKAGE TYPE Large Thru-Hole Small Thru-Hole Small SMT Small SMT Small SMT Small SMT
TRANSFORMER VENDOR INFORMATION Pulse Corporate Office 12220 World Trade Drive San Diego, CA 92128 Tel: (858)-674-8100 FAX: (858)-674-8262 Europe 1 & 2 Huxley Road The Surrey Research Park Guildford, Surrey GU2 5RE United Kingdom Tel: 44-1483-401700 FAX: 44-1483-401701 Asia 150 Kampong Ampat #07-01/02 KA Centre Singapore 368324 Tel: 65-287-8998 FAX: 65-280-0080 Transpower Technologies, Inc. Corporate Office Park Center West Building 9805 Double R Blvd, Suite # 100 Reno, NV 89511 (800)500-5930 or (775)852-0140 Halo Electronics Corporate Office P.O. Box 5826 Redwood City, CA 94063 Tel: (650)568-5800 FAX: (650)568-6165
Email: info@haloelectronics.com Website: http://www.haloelectronics.com
Email: info@trans-power.com Website: http://www.trans-power.com
Website: http://www.pulseeng.com
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XRT73L03A
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REV. 2.0.4
3.0 THE RECEIVE SECTION Figure 13 indicates the Receive Section consists of the following blocks: * AGC/Equalizer * Peak Detector * Slicer * Clock Recovery PLL * Data Recovery * HDB3/B3ZS Decoder The purpose of the Receive Section is to take an incoming attenuated/distorted bipolar signal from the line and encode it back into the TTL/CMOS format
where it can be received and processed by the Terminal Equipment. 3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L03A TO THE LINE The design of the Receive Circuitry allows for transformer-couple or capacitive-couple the Receive Section to the line. The specification documents for E3, DS3, and STS-1 all specify 75 Ohm termination loads when transmitting over coaxial cable. The recommended method to interface the Receive Section to the line in a manner is shown in Figure 22 and Figure 23.
FIGURE 22. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L03A TO THE LINE (TRANSFORMER-COUPLING)
RTIP_(n) Channel (n) R1 37.4 T1 C1 0.01uf J1 BNC
RxPOS_(n) RxNEG_(n) RxClk_(n)
RPOS_(n) RNEG_(n) RxClk_(n)
R2 37.4
1:1
RRing_(n) Only One Channel Shown
35
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
Figure 23 presents the recommended schematic for capacitive-coupling each Receive Section of the XRT73L03A to the line. FIGURE 23. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L03A TO THE LINE (CAPACITIVE-COUPLING)
C1 0.01uf RTIP_(n) Channel (n) R1 75 J1 BNC
RxPOS_(n) RxNEG_(n) RxClk_(n)
RPOS_(n) RNEG_(n) RxClk_(n)
C2 0.01uf RRing_(n) Only One Channel Shown
3.2 THE RECEIVE EQUALIZER BLOCK The purpose of this block is to equalize the incoming distorted signal due to cable loss. The Receive
Equalizer attempts to restore the shape of the line signal so that the transmitted data and clock can be recovered reliably.
36
XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
.
FIGURE 24. THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER
Transmitting Terminal
0 to 450 feet of Cable
Digital Cross-Connect System
Pulses that are compliant to the Isolated DSX-3 or STSX-1 Pulse Template Requirement
DSX-3 or STSX-1
0 to 450 feet of Cable
Receiving Terminal
3.2.1 izer
Guidelines for Setting the Receive Equal-
recommend enabling the Receive Equalizer for these applications. 3.2.1.1.1 The Use of the Receive Equalizer in a Typical DS3 or STS-1 Application Most System Manufacturers of equipment supporting DS3 and STS-1 lines, interface their equipment to either a DSX-3 or STSX-1 Cross-Connect. While installing their equipment the Transmit Line Build-Out circuit is set to the proper setting that makes the transmit output pulse compliant with the Isolated DSX-3 or STSX-1 Pulse Template requirements. For the XRT73L03A device, this is achieved by setting the TXLEV_(n) input pin or bit-field to the appropriate level. When the System Manufacturer is interfacing the Receive Section of the XRT73L03A to the Cross-Connect, they should be aware of the following facts: 1. All DS3 or STS-1 line signals that are present at either the DSX-3 or the STSX-1 Cross Connect are required to meet the Isolated Pulse Template
This data sheet presents guidelines for setting the Receive Equalizer, for the following conditions. 1. If the overall cable length, from the local Receiving Terminal to the Remote Transmitting Terminal is NOT known. 2. If the overall cable length, from the Local Receiving Terminal to the remote Transmitting Terminal is known. 3.2.1.1 If the Overall Cable Length is NOT Known This section presents recommendations on what state to set the Receive Equalizer when the overall cable-length, from the local Receiving Terminal to the remote Transmitting Terminal is NOT known. For DS3, STS-1 and E3 applications, enable the Receive Equalizer by setting either the REQEN_(n) input pin "high" or the REQEN_(n) bit-field to "1". The remainder of this section provides an explanation why we
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Requirements per Bellcore GR-499-CORE for DS3 applications, or Bellcore GR-253-CORE for STS-1 applications. 2. Bellcore documents state that the amplitude of these pulses at the DSX-3 or STSX-1 location can range in amplitude from 360mVpk to 850mVpk. 3. Bellcore documents stipulate that the Receiving Terminal must be able to receive the pulse template compliant line signal over a cable length of 0 to 450 feet from the DSX-3 or the STSX-1 Cross-Connect location. These facts are reflected in Figure 24. Design Considerations for DS3 and STS-1 Applications When installing equipment into environments depicted in Figure 24, the system installation personnel may be able to determine the cable length between the local terminal equipment and the DSX-3/STSX-1 Cross-Connect Patch-Panel. The cable length between the local terminal equipment and the DSX-3/ STSX-1 Cross-Connect Patch Panel ranges between 0 and 450 feet. It is extremely unlikely that the system installation personnel will know the cable length between the DSX-3/STSX-1 Cross-Connect Patch-Panel and the remote terminal equipment. Therefore, we recommend that the Receive Equalizer be enabled by setting the REQEN_(n) input pin or bit-field to "1". The only time that the Receive Equalizer should be disabled is when there is an off-chip equalizer in the Receive path between the DSX-3/STSX-1 CrossConnect and the RTIP_(n)/RRING_(n) input pins, or in applications where the Receiver is directly monitoring the transmit output signal directly. 3.2.1.2 tions Design Considerations for E3 Applica-
NOTE: The results of extensive testing indicates that when the Receive Equalizer is enabled, the XRT73L03A device is capable of receiving an E3 line signal with anywhere from 0 to 12dB of cable loss over the Industrial Temperature range.
* Design Considerations for E3 Applications or if the Overall Cable Length is known If during System Installation the overall cable length is known, then in order to optimize the performance of the XRT73L03A in terms of receive intrinsic jitter, etc., enable or disable the Receive Equalizer based upon the following recommendations: The Receive Equalizer should be turned ON if the Receive Section of a given channel is going to receive a line signal with an overall cable length of 300 feet or greater. Conversely, turn OFF the Receive Equalizer if the Receive Section of a given channel is going to receive a line signal over a cable length of less than 300 feet.
NOTES: 1. If the Receive Equalizer block is turned ON when it is receiving a line signal over short cable length, the received line signal may be over-equalized which could degrade performance by increasing the amount of jitter that exists in the recovered data and clock signals or by creating bit-errors 2. The Receive Equalizer has been designed to counter the frequency-dependent cable loss that a line signal experiences as it travels from the transmitting terminal to the receiving terminal. However, the Receive Equalizer was not designed to counter flat loss where all of the Fourier frequency components within the line signal are subject to the same amount of attenuation. Flat loss is handled by the AGC block.
Disable the Receive Equalizer block by doing either of the following. a. Operating in the Hardware Mode Set the REQEN_(n) input pin "Low". b. Operating in the HOST Mode Write a "0" to the REQEN_(n) bit-field within Command Register CR2, as illustrated below.
In E3 System installation, it is recommended that the Receive Equalizer of the XRT73L03A device be enabled by pulling the REQEN_(n) input pins "High" or by setting the REQEN_(n) bit-fields to "1".
COMMAND REGISTER CR2-(n)
D4 Reserved X D3 ENDECDIS_(n) X D2 ALOSDIS_(n) X D1 DLOSDIS_(n) X D0 REQEN_(n) 0
3.3 CLOCK RECOVERY PLL
The purpose of the Clock Recovery PLL is to track the incoming Dual-Rail data stream and to derive and generate a recovered clock signal.
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It is important to note that the Clock Recovery PLL requires a line rate clock signal at the EXClk_(n) input pin. The Clock Recovery PLL operates in one of two modes: * The Training Mode. * The Data/Clock Recovery Mode 3.3.1 The Training Mode If a given channel is not receiving a line signal via the RTIP and RRing input pins, or if the frequency difference between the line signal and that applied via the EXClk_(n) input pin exceeds 0.5%, then the channel operates in the Training Mode. When the channel is operating in the Training Mode, it does the following: a. Declare a Loss of Lock indication by toggling its respective RLOL_(n) output pin "High". b. Output a clock signal via the RxClk_(n) output pins which is derived from the signal applied to the EXClk_(n) input pin. 3.3.2 The Data/Clock Recovery Mode If the frequency difference between the line signal and that applied via the EXClk_(n) input pin is less than 0.5%, then the channel operates in the Data/ Clock Recovery mode. In this mode, the Clock Recovery PLL locks onto the line signal via the RTIP and RRing input pins. 3.4 THE HDB3/B3ZS DECODER The Remote Transmitting Terminal typically encodes the line signal into some sort of Zero Suppression FIGURE 25. AN EXAMPLE OF B3ZS DECODING
00 V Line Signal
Line Code (e.g., HDB3 for E3, and B3ZS for DS3 and STS-1). The purpose of this encoding activity was to aid in the Clock Recovery process of this data within the Near-End Receiving Terminal. However, once the data has made it across the E3, DS3 or STS-1 Transport Medium and has been recovered by the Clock Recovery PLL, it is now necessary to restore the original content of the data. Hence, the purpose of the HDB3/B3ZS Decoding block is to restore the data transmitted over the E3, DS3 or STS-1 line to its original content prior to Zero Suppression Coding. 3.4.1 B3ZS Decoding (DS3/STS-1 Applications) If the XRT73L03A is configured to operate in the DS3 or STS-1 Modes, then the HDB3/B3ZS Decoding Blocks performs B3ZS Decoding. When the Decoders are operating in this mode, each of the Decoders parses through its respective incoming Dual-Rail data and checks for the occurrence of either a "00V" or a "B0V" pattern. If the B3ZS Decoder detects this particular pattern, then it substitutes these bits with a "000" pattern.
NOTE: If the B3ZS Decoder detects any bipolar violations that is not in accordance with the B3ZS Line Code format, or if the B3ZS Decoder detects a string of 3 (or more) consecutive "0's" in the incoming line signal, then the B3ZS Decoder flags this event as a Line Code Violation by pulsing the LCV output pin "High".
Figure 25 illustrates the B3ZS Decoder at work with two separate Zero Suppression patterns in the incoming Dual-Rail Data Stream.
B 0V RCLK RPOS RNEG Data 01011000101111011011001110001
3.4.2 HDB3 Decoding (E3 Applications) If the XRT73L03A is configured to operate in the E3 Mode, then each of the HDB3/B3ZS Decoding Blocks performs HDB3 Decoding. When the Decoders are operating in this mode, they each parse through the
incoming Dual-Rail data and check for the occurrence of either a "000V" or a "B00V" pattern. If the HDB3 Decoder detects this particular pattern, then it substitutes these bits with a "0000" pattern.
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Figure 26 illustrates the HDB3 Decoder at work with two separate Zero Suppression patterns, in the incoming Dual-Rail Data Stream. FIGURE 26. AN EXAMPLE OF HDB3 DECODING
00 0 V Line Signal B 00 V RCLK RPOS RNEG Data 0 1011000001111011011001100001
NOTE: If the HDB3 Decoder detects any bipolar violation (e.g., "V") pulses that is not in accordance with the HDB3 Line Code format, or if the HDB3 Decoder detects a string of 4 (or more) "0's" in the incoming line signal, then the HDB3 Decoder flags this event as a Line Code Violation by pulsing the LCV output pin "High".
3.4.3 Configuring the HDB3/B3ZS Decoder The XRT73L03A can enable or disable the HDB3/ B3ZS Decoder blocks by either of the following means. a. Operating in the HOST Mode Enable the HDB3/B3ZS Decoder block of Channel(n) by writing a "0" into the (SR/DR)_(n) bit-field within Command Register CR3-(n), as illustrated below.
COMMAND REGISTER CR2-(n)
D4 Reserved X D3 ENDECDIS_(n) 0 D2 ALOSDIS_(n) X D1 DLOSDIS_(n) X D0 REQEN_(n) 1
b. Operating in the Hardware Mode To globally enable all HDB3/B3ZS Decoder blocks in the XRT73L03A, pull the ENDECDIS input pin "Low". To globally disable all HDB3/B3ZS Decoder blocks in the XRT73L03A and configure the XRT73L03A to transmit and receive in an AMI format, pull the ENDECDIS input pin "High". 3.5 LOS DECLARATION/CLEARANCE Each channel of the XRT73L03A contains circuitry that monitors the following two parameters associated with the incoming line signals. 1. The amplitude of the incoming line signal via the RTIP and RRing inputs. 2. The number of pulses detected in the incoming line signal within a certain amount of time.
If a given channel of the XRT73L03A determines that the incoming line signal is missing due to either insufficient amplitude or a lack of pulses in the incoming line signal, it declares a Loss of Signal (LOS) condition. The channel declares the LOS condition by toggling its respective RLOS_(n) output pin "High" and by setting its corresponding RLOS_(n) bit field in Command Register 0 or Command Register 8 to "1". Conversely, if the channel determines that the incoming line signal has been restored (e.g., there is sufficient amplitude and pulses in the incoming line signal), it clears the LOS condition by toggling its respective RLOS_(n) output pin "Low" and setting its corresponding RLOS_(n) bit-field to "0". In general, the LOS Declaration/Clearance scheme that is employed in the XRT73L03A is based upon ITU-T Recommendation G.775 for both E3 and DS3 applications. 40
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3.5.1 The LOS Declaration/Clearance Criteria for E3 Applications When the XRT73L03A is operating in the E3 Mode, a given channel declares an LOS Condition if its receive line signal amplitude drops to -35dB or below.
Further, the channel clears the LOS Condition if its receive line signal amplitude rises back to -15dB or above. Figure 27 illustrates the signal levels at which each channel of the XRT73L03A declares and clears LOS.
FIGURE 27. THE SIGNAL LEVELS THAT THE XRT73L03A DECLARES AND CLEARS LOS
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB -15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
Timing Requirements associated with Declaring and Clearing the LOS Indicator The XRT73L03A was designed to meet the ITU-T G.775 specification timing requirements for declaring and clearing the LOS indicator. In particular, a channel declares an LOS between 10 and 255 UI (or E3
bit-periods) after the actual time the LOS condition occurred. Further, the channel clears the LOS indicator within 10 to 255 UI after restoration of the incoming line signal. Figure 28 illustrates the LOS Declaration and Clearance behavior in response to the Loss of Signal event and then the restoration of the signal.
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TORATION OF
FIGURE 28. THE BEHAVIOR OF THE LOS OUTPUT INDICATOR IN RESPONSE TO THE LOSS OF SIGNAL AND THE RESSIGNAL
Actual Occurrence of LOS Condition RTIP/ RRing Line Signal is Restored
10 UI
255 UI
Time Range for LOS Declaration
10 UI
255 UI
RLOS Output Pin 0 UI G.775 Compliance 0 UI Time Range for LOS Clearance G.775 Compliance
3.5.2 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications When the XRT73L03A is operating in the DS3 or STS-1 Mode, then each channel declares and clears LOS based upon the following two criteria. * Analog LOS (ALOS) Declaration/Clearance Criteria * Digital LOS (DLOS) Declaration/Clearance Criteria In the DS3 Mode, the LOS output (RLOS) is simply the logical "OR" of the ALOS and DLOS states.
1. The Analog LOS (ALOS) Declaration/Clearance Criteria A channel declares an Analog LOS (ALOS_(n)) Condition if the amplitude of the incoming line signal drops below a specific amplitude as defined by the voltage at the LOSTHR input pin, and whether the Receive Equalizer is enabled or not. Table 5 presents the various voltage levels at the LOSTHR input pin, the state of the Receive Equalizer and the corresponding ALOS (Analog LOS) threshold amplitudes.
TABLE 5: THE ALOS (ANALOG LOS) DECLARE AND CLEAR THRESHOLDS FOR A GIVEN SETTING OF LOSTHR & REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION DS3 STS-1 REQEN SETTING 1 0 1 0 LOSTHR SETTING 1 1 1 1 SIGNAL LEVEL TO DECLARE ALOS <22mV <17mV <25mV <20mV SGNAL LEVEL TO CLEAR ALOS >90mV >70mV >115mV >90mV
Declaring ALOS A channel(n) declares ALOS_(n) whenever the amplitude of the receive line signal falls below the Signal Level to Declare ALOS levels, as specified inTable 5. Clearing ALOS_(n) A channel(n) clears ALOS_(n) whenever the amplitude of the receive line signal increases above the
Signal Level to Clear ALOS levels, as specified in Table 5. There is approximately a 2dB hysteresis in the received signal level that exists between declaring and clearing ALOS_(n) in order to prevent chattering in the RLOS_(n) output signal. Monitoring the State of ALOS_(n)
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If the XRT73L03A is operating in the HOST Mode, the state of ALOS_(n) of Channel(n) can be polled or
monitored by reading in the contents of Command Register CR0. .
COMMAND REGISTER CR0-(n)
D4 RLOL_(n) Read Only D3 RLOS_(n) Read Only D2 ALOS_(n) Read Only D1 DLOS_(n) Read Only D0 DMO_(n) Read Only
If the ALOS_(n) bit-field contains a "1", then the corresponding Channel(n) is currently declaring an ALOS condition. Conversely, if the ALOS_(n) bit-field contains a "0", then the channel is not currently declaring an ALOS condition. Disabling the ALOS Detector
For debugging purposes, it may be useful to disable the ALOS Detector. If the XRT73L03A is operating in the HOST Mode, disable the Channel(n) ALOS Detector by writing a "1" into the ALOSDIS_(n) bit-field in Command Register CR2.
COMMAND REGISTER CR2-(n)
D4 Reserved X D3 ENDECDIS_(n) X D2 ALOSDIS_(n) 1 D1 DLOSDIS_(n) X D0 REQEN_(n) X
2. The Digital LOS (DLOS) Declaration/Clearance Criteria A given channel(n) declares a Digital LOS (DLOS_(n)) condition if the XRT73L03A detects 16032 or more consecutive "0's" in the incoming data. The channel clears DLOS if it detects four consecutive sets of 32 bit-periods, each of which contains at least 10 "1's" (e.g., average pulse density of greater than 33%). Monitoring the State of DLOS If the XRT73L03A is operating in the HOST Mode the state of DLOS_(n) of Channel(n) can be polled or monitored by reading in the contents of Command Register CR0.
D4
COMMAND REGISTER CR0-(n)
D3 D2 D1 D0
RLOL_(n) RLOS_(n) ALOS_(n) DLOS_(n) DMO_(n) Read Only Read Only Read Only Read Only Read Only
If the DLOS_(n) bit-field contains a "1", then the corresponding channel(n) is currently declaring a DLOS condition. Conversely, if the DLOS_(n) bit-field contains a "0", then the channel(n) is currently declaring the DLOS condition. Disabling the DLOS Detector For debugging purposes, it is useful to disable the DLOS_(n) detector. If the XRT73L03A is operating in the HOST Mode, the DLOS Detector can be disabled by writing a "1" into the DLOSDIS_(n) bit-field in Command Register CR2.
COMMAND REGISTER CR2-(n)
D4 Reserved X D3 ENDECDIS_(n) X D2 ALOSDIS(n) X D1 DLOSDIS(n) 1 D0 REQEN(n) X
NOTE: Setting both the ALOSDIS_(n) and DLOSDIS_(n) bit-fields to "1" disables LOS Declaration by Channel(n).
3.5.3 Muting the Recovered Data while the LOS is being Declared In some applications it is not desirable for a channel within the E3/DS3/STS-1 LIU to recover data and
route it to the Receiving Terminal while the channel is declaring an LOS condition. Consequently, the XRT73L03A includes an LOS Muting feature. This feature, if enabled, causes a given channel to halt transmission of the recovered data to the Receiving Terminal while the LOS condition is "true". In this case, the RPOS_(n) and RNEG_(n) output pins are 43
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forced to "0". Once the LOS condition has been cleared, then the channel(n) resumes normal transmission of the recovered data to the Receiving Terminal. This feature is available whenever XRT73L03A is operating in the HOST Mode or Hardware Mode. a. Operating in the Hardware Mode.
The Muting upon LOS feature is enabled by pulling the LOSMUTEN output pin "High". This enables the Muting upon LOS feature globally for all channels. b. Operating in the HOST Mode. The Muting upon LOS feature for each Channel can be enabled by writing a "1" into the LOSMUT_(n) bitfield within Command Register 3.
COMMAND REGISTER CR3-(n)
D4 (SR/DR)_(n) X D3 LOSMUT_(n) 1 D2 RxOFF_(n) x D1 RxClk_(n)INV x D0 Reserved x
NOTE: This step only enables the Muting upon LOS feature within Channel(n).
3.6 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT Each channel takes the Recovered Timing and Data information, converts it into CMOS levels and routes it to the Receiving Terminal Equipment via the RPOS_(n), RNEG_(n) and RxClk_(n) output pins. Each channel can deliver the recovered data and clock information to the Receiving Terminal in either a Single-Rail or Dual-Rail format.
3.6.1 Routing Dual-Rail Format Data to the Receiving Terminal Equipment Whenever a channel delivers Dual-Rail format to the Terminal Equipment, it does so via the following signals. * RPOS_(n) * RNEG_(n) * RxClk_(n) Figure 29 illustrates the typical interface for the transmission of data in a Dual-Rail Format from the Receive Section of a channel to the Receiving Terminal Equipment.
.
FIGURE 29. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT, FROM THE RECEIVE SECTION OF THE XRT73L03A TO THE RECEIVING TERMINAL EQUIPMENT
RxPOS Terminal Equipment (E3/DS3 or STS-1 Framer) RxNEG RxClk
RPOS RNEG RxClk
Receive Logic Block
Exar E3/DS3/STS-1 LIU
The manner that a given channel transmits Dual-Rail data to the Receiving Terminal Equipment is de-
scribed below and illustrated in Figure 30. Each
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channel(n) typically updates the data on the RPOS_(n) and RNEG_(n) output pins on the rising edge of RxClk_(n). FIGURE 30. HOW THE XRT73L03A OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS
RPOS
RNEG RxClk
RxClk_(n) is the Recovered Clock signal from the incoming Received line signal. As a result, these clock signals are typically 34.368 MHz for E3 applications, 44.736 MHz for DS3 applications and 51.84 MHz for SONET STS-1 applications. In general, if a given channel received a positive-polarity pulse in the incoming line signal via the RTIP_(n) and RRing_(n) input pins, then the channel pulses its corresponding RPOS_(n) output pin "High". Conversely, if the channel received a negative-polarity pulse in the incoming line signal via the RTIP_(n) and RRing_(n) input pins, then the channel(n) pulses its corresponding RNEG_(n) output pin "High". Inverting the RxClk_(n) outputs Each channel can invert the RxClk_(n) signals with respect to the delivery of the RPOS_(n) and
RNEG_(n) output data to the Receiving Terminal Equipment. This feature may be useful for those customers whose Receiving Terminal Equipment logic design is such that the RPOS_(n) and RNEG_(n) data must be sampled on the rising edge of RxClk_(n). Figure 31 illustrates the behavior of the RPOS_(n), RNEG_(n) and RxClk_(n) signals when the RxClk_(n) signal has been inverted. In the Hardware Mode: Setting the RxClkINV pin "High" results in all channels of the XRT73L03A to output the recovered data on RPOS_(n) and RNEG_(n) on the falling edge of RxClk_(n). Setting this pin "Low" results in the recovered data on RPOS_(n) and RNEG_(n) to output on the rising edge of RxClk_(n).
FIGURE 31. THE BEHAVIOR OF THE RPOS, RNEG, AND RXCLK SIGNALS WHEN RXCLK IS INVERTED
RPOS
RNEG RxClk
a. Operating in the HOST Mode
In order to configure a channel(n) to invert the RxClk_(n) output signal, the XRT73L03A must be operating in the HOST Mode.
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To invert RxClk_(n), associated with Channel(n), write a "1" into the RxClk_(n)INV bit-field within Command Register CR-3. COMMAND REGISTER CR3-(n)
D4 (SR/DR)_(n) X D3 LOSMUT_(n) X D2 RxOFF_(n) X D1 RxClk_(n)INV 1 D0 Reserved X
b. Operating in the Hardware Mode Setting the RxClkINV input pin "High" inverts all the RxClk_(n) output signals. 3.6.2 Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment
To route Single-Rail format data (e.g., a binary data stream) from the Receive Section of a channel to the Receiving Terminal Equipment, do the following. a. Operating in the HOST Mode To configure Channel(n) to output Single-Rail data to the Terminal Equipment, write a "1" into the (SR/ DR)_(n) bit-field within Command Register CR3-(n).
COMMAND REGISTER CR3-(n)
D4 (SR/DR)_(n) 1 D3 LOSMUT_(n) X D2 RxOFF_(n) X D1 RxClk_(n)INV X D0 Reserved X
The configured channel outputs Single-Rail data to the Receiving Terminal Equipment via its corresponding RPOS_(n) and RxClk_(n) output pins, as illustrated in Figure 32 and Figure 33. b. Operating in the Hardware Mode The XRT73L03A is configure to output Dual-Rail data from the Receive Sections of all channels by pulling the (SR/DR) pin to GND.
The XRT73L03A is configure to output Single-Rail data from the Receive Sections of all channels by pulling the (SR/DR) pin to VDD.
NOTE: When the XRT73L03A is operating in the Hardware Mode, the setting of the (SR/DR) input pin applies globally to all channels.
.
FIGURE 32. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A SINGLE-RAIL FORMAT FROM THE RECEIVE SECTION OF THE XRT73L03A TO THE RECEIVING TERMINAL EQUIPMENT
RxPOS
RPOS
TerminalEquipment (E3/DS3 or STS-1 Framer)
RxClk
RxClk
Receive Logic Block
Exar E3/DS3/STS-1 LIU
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TING
FIGURE 33. THE BEHAVIOR OF THE RPOS AND RXCLK OUTPUT SIGNALS WHILE THE XRT73L03A IS TRANSMITSINGLE-RAIL DATA TO THE RECEIVING TERMINAL EQUIPMENT
RPOS RxClk
NOTE: The RNEG_(n) output pin is internally tied to Ground whenever this feature is implemented.
a. Operating in the Hardware Mode Shut off the Receive Sections by pulling the RxOFF input pin "High". Turn on the Receiver Sections by pulling the RxOFF input pin to "Low". b. Operating in the HOST Mode Shut off the Receive Sections by writing a "1" into the RxOFF bit-field within Command Register CR3-(n). COMMAND REGISTER CR3-(n)
D4 D3 D2 D1 D0
3.7 SHUTTING OFF THE RECEIVE SECTION The Receive Section of each channel in the XRT73L03A can be shut off. This feature may come in handy in some redundant system designs. Particularly, in those designs where the Receive Termination within the Secondary LIU Line Card has been switched-out and is not receiving any traffic in parallel with the Primary Line Card. In this case, having the LIU on the Secondary Line Card consume the normal amount of current is a waste of power. This feature can permit powering down the Receive Section of the LIU's on the Secondary Line Card which reduces their power consumption by approximately 80%
LOSMUT_(n) RxOFF_(n) RxClk_(n)INV Reserved (SR/ DR)_(n)
X
X
1
X
X
Turn on the Receive Section of Channel(n) by writing a "0" into the RxOFF bit-field within Command Register CR3-(n).
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4.0 DIAGNOSTIC FEATURES OF THE XRT73L03A The XRT73L03A supports equipment diagnostic activities by supporting the following Loop-Back modes within each channel. * Analog Local Loop-Back. * Digital Local Loop-Back * Remote Loop-Back
NOTE: In this data sheet we use the convention that Channel(n) refers to either channel 0, 1 or 2. Similarly, specific input and output pins uses this convention to denote which channel it is associated with.
4.1 THE ANALOG LOCAL LOOP-BACK MODE When a given channel is configured to operate in the Analog Local Loop-Back Mode, the channel ignores any signals that are input to its RTIP_(n) and RRing_(n) input pins. The Transmitting Terminal Equipment transmits clock and data into this channel
via the TPData_(n), TNData_(n) and TxClk_(n) input pins. This data is processed through the Transmit Clock Duty Cycle Adjust PLL and the HDB3/B3ZS Encoder. Finally, this data is output to the line via the TTIP_(n) and TRing_(n) output pins. Additionally, this data which is being output via the TTIP_(n) and TRing_(n) output pins is also looped back into the Attenuator/Receive Equalizer Block. Consequently, this data is processed through the entire Receive Section of the channel. After this post-Loop-Back data has been processed through the Receive Section it outputs to the Near-End Receiving Terminal Equipment via the RPOS_(n), RNEG_(n) and RxClk_(n) output pins. Figure 34 illustrates the path that the data takes when the channel is configured to operate in the Analog Local Loop-Back Mode.
FIGURE 34. A CHANNEL OPERATING IN THE ANALOG LOCAL LOOP-BACK MODE
RLOL_(n) EXClk_(n)
RTIP_(n) RRing_(n) REQEN_(n)
AGC/ Equalizer Peak Detector
Slicer
Clock Recovery Data Recovery LOS Detecto r
Invert
RxClk_(n)
HDB3/ B3ZS Decoder
RPOS_(n) RNEG_(n) LCV_(n) ENDECDIS RLOS_(n)
LOSTHR_(n) SDI SDO SClk CS REGR Serial Processor Interface
Analog Local Loop-Back Path
Loop MUX
LLB_(n) RLB_(n) TAOS_(n)
TTIP_(n) Pulse Shaping TRing_(n) TxLEV_(n) TxOFF_(n) DMO_(n)
HDB3/ B3ZS Encoder
Transmit Logic Duty Cycle Adjust
TPData_(n) TNData_(n) TxClk_(n) MTIP_(n) MRing_(n)
Device Monitor
Notes: 1. (n) = 0, 1 or 2 for respective Channels 2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Configure a given channel to operate in the Analog Local Loop-Back Mode by employing either one of the following two steps
a. Operating in the HOST Mode
NOTE: See for a description of Command Registers and Addresses for the different channels.
To configure Channel (n) to operate in the Analog Local Loop-Back Mode, write a "1" into the LLB_(n) bitfield and a "0" into the RLB_(n) bit-field within Command Register CR4.
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COMMAND REGISTER CR4-(n)
D4 X X D3 STS-1/DS3_(n) X D2 E3_(n) X D1 D0
LLB_(n) RLB_(n) 1 0
b. Operating in the Hardware Mode To configure Channel (n) to operate in the Analog Local Loop-Back Mode, set the LLB_(n) input pin "High" and the RLB_(n) input pin "Low". 4.2 THE DIGITAL LOCAL LOOP-BACK MODE. When a given channel is configured to operate in the Digital Local Loop-Back Mode, the channel ignores
any signals that are input to the RTIP and RRing input pins. The Transmitting Terminal Equipment transmits clock and data into the XRT73L03A via the TPData, TNData and TxClk input pins. This data is processed through the Transmit Clock Duty Cycle Adjust PLL and the HDB3/B3ZS Encoder block. At this point, this data is looped back to the HDB3/B3ZS Decoder block. After this post-Loop-Back data has been processed through the HDB3/B3ZS Decoder block, it outputs to the Near-End Receiving Terminal Equipment via the RPOS, RNEG and RxClk output pins. Figure 35 illustrates the path that the data takes when the chip is configured to operate in the Digital Local Loop-Back Mode.
FIGURE 35. THE DIGITAL LOCAL LOOP-BACK PATH WITHIN A GIVEN CHANNEL
RLOL_(n) EXClk_(n)
RTIP_(n) RRing_(n)
AGC/ Equalizer Peak Detector
Slicer
Clock Recovery Data Recovery
Invert
RxClk_(n)
REQEN_(n)
LOSTHR_(n) SDI SDO SClk CS REGR Serial Processor Interface
LOS Detector
HDB3/ B3ZS Decoder
RPOS_(n) RNEG_(n) LCV(_n) ENDECDIS RLOS_(n) LLB_(n) RLB_(n) TAOS_(n)
Digital Local Loop-Back Path
Loop MUX
TTIP_(n) Pulse Shaping TRing_(n) TxLEV_(n) TxOFF_(n) DMO_(n)
HDB3/ B3ZS Encoder
Transmit Logic Duty Cycle Adjust
TPData(_n) TNData_(n) TxClk_(n) MTIP_(n) MRing(_n)
Device Monitor
Notes: 1. (n) = 0, 1 or 2 for respective Channels 2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Configure a channel to operate in the Digital Local Loop-Back Mode by employing either one of the following two-steps: a. Operating in the Host Mode
To configure Channel (n) to operate in the Digital Local Loop-Back Mode, write a "1" into both the LLB and RLB bit-fields within Command Register CR4-(n). COMMAND REGISTER CR4-(n)
D4 X X D3 STS-1/DS3_(n) X D2 E3_(n) X D1 D0
LLB_(n) RLB_(n) 1 1
b. Operating in the Hardware Mode.
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To configure Channel (n) to operate in the Digital Local Loop-Back Mode, pull both the LLB input pin and the RLB input pin "High". 4.3 THE REMOTE LOOP-BACK MODE When a given channel is configured to operate in the Remote Loop-Back Mode, the channel ignores any signals that are input to the TPData and TNData input pins. The channel receives the incoming line signal via the RTIP and RRing input pins. This data is processed through the entire Receive Section and is out-
put to the Receive Terminal Equipment via the RPOS, RNEG and RxClk output pins. Additionally, this data is also internally looped back into the Pulse-Shaping block within the Transmit Section. At this point, this data is routed through the remainder of the Transmit Section of the channel and transmitted out onto the line via the TTIP_(n) and TRing_(n) output pins. Figure 36 illustrates the path that the data takes when the chip is configured to operate in the Remote LoopBack Mode.
FIGURE 36. THE REMOTE LOOP-BACK PATH, WITHIN A GIVEN CHANNEL
RLOL_(n) EXClk_(n)
RTIP_(n) RRing_(n) REQEN_(n)
AGC/ Equalizer Peak Detector
Slicer
Clock Recovery Data Recovery
Invert
RxClk_(n)
LOSTHR_(n) SDI SDO SClk CS REGR Serial Processor Interface
LOS Detector
HDB3/ B3ZS Decoder
RPOS_(n) RNEG_(n) LCV_(n) ENDECDIS
Remote Loop-Back Path
RLOS_(n) Loop MUX LLB_(n) RLB_(n) TAOS_(n)
TTIP_(n) Pulse Shaping TRing_(n) TxLEV_(n) TxOFF_(n) DMO_(n)
HDB3/ B3ZS Encoder
Transmit Logic Duty Cycle Adjust
TPData_(n) TNData_(n) TxClk_(n) MTIP_(n) MRing_(n)
Device Monitor
Notes: 1. (n) = 0, 1 or 2 for respective Channels 2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Configure a channel to operate in the Remote LoopBack Mode by employing either one of the following two steps a. Operating in the HOST Mode To configure Channel (n) to operate in the Remote Loop-Back Mode, write a "1" into the RLB bit-field, and a "0" into the LLB bit-field, within Command Register CR4.
COMMAND REGISTER CR4-(n)
D4 X X D3 STS-1/DS3_(n) X D2 E3_(n) X D1 LLB_(n) 0 D0 RLB_(n) 1
b. Operating in the Hardware Mode To configure Channel(n) to operate in the Remote Loop-Back Mode, pull both the RLB_(n) input pin to "High" and the LLB_(n) input pin to "Low".
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4.4 TXOFF FEATURES The Transmit Section of each Channel in the XRT73L03A can be shut off. When this feature is invoked, the Transmit Section of the configured channel is shut-off and the Transmit Output signals (e.g., TTIP_(n) and TRing_(n)) is tri-stated. This feature is useful for system redundancy conditions or during diagnostic testing. a. Operating in the Hardware Mode Shut off the Transmit Driver concurrently within all Channels by toggling the TxOFF input pin "High". Turn on the Transmit Driver by toggling the TxOFF input pin "Low". b. Operating in the HOST Mode Turn off the Transmit Driver within Channel(n) by setting the TxOFF_(n) bit-field within Command Register CR1-(n) to "1".
COMMAND REGISTER CR1-(n)
D4 D3 D2 D1 D0
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n)
1
X
X
X
X
Writing a "0" into this bit-field enables the Channel(n)Transmit Driver.
NOTE: In order to permit a system designed for redundancy to quickly shut-off a defective line card and turn-on the back-up line card, the XRT73L03A was designed such that either Transmitter can quickly be turned-on or turned-off by toggling the TxOFF input pins. This approach is much quicker then setting the TxOFF_(n) bit-fields via the Microprocessor Serial Interface.
Table 6 presents a Truth Table which relates the setting of the TxOFF external pin and bit-field for a channel to the state of the Transmitter. This table applies to all Channels of the XRT73L03A.
TABLE 6: THE RELATIONSHIP BETWEEN THE TXOFF INPUT PIN, THE TXOFF BIT FIELD AND THE STATE OF THE TRANSMITTER
STATE OF THE TXOFF INPUT PIN LOW LOW HIGH HIGH STATE OF THE TXOFF BIT FIELD 0 1 0 1 STATE OF THE TRANSMITTER ON (Transmitter is Active) OFF (Transmitter is Tri-Stated) OFF (Transmitter is Tri-Stated) OFF (Transmitter is Tri-Stated)
To control the state of all transmitters via the Microprocessor Serial interface, connect the TxOFF input pin to GND. 4.5 THE TRANSMIT DRIVE MONITOR FEATURES The Transmit Drive Monitor is used to monitor the line in the Transmit Direction for the occurrence of fault conditions such as a short circuit on the line, a defective Transmit Drive in the XRT73L03A or another LIU.
Activate the Channel(n) Transmit Drive Monitor by connecting the MTIP_(n) pin to the TTIP_(n) line through a 270 Ohm resistor connected in series, and connecting the MRing_(n) pin to the TRing_(n) line through a 270 Ohm resistor connected in series. Such an approach is illustrated in Figure 37.
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FIGURE 37. THE XRT73L03A EMPLOYING THE TRANSMIT DRIVE MONITOR FEATURES
J1 BNC TTIP_(n) R1 = 31.6 TRing_(n)
TxPOS_(n) TxNEG_(n) TxLineClk_(n)
TPData_(n) TNData_(n) TxClk_(n)
MTIP_(n) R3 = 270 MRing_(n) R4 = 270 Channel (n) Only One Channel Shown
R2 = 31.6
1:1
When the Transmit Drive Monitor circuitry within a given line is connected to the line, as illustrated in Figure 37, then it monitors the line for transitions. As long as the Transmit Drive Monitor circuitry detects transitions on the line via the MTIP_(n) and MRing_(n) pins, then it keeps the DMO (Drive Monitor Output) signal "Low". However, if the Transmit Drive Monitor circuit detects no transitions on the line for 128+32 TxClk periods, then the DMO (Drive Monitor Output) signal toggles "High".
NOTE: The Transmit Drive Monitor circuit does not have to be used to operate the Transmit Section of the XRT73L03A. This is purely a diagnostic feature.
b. Operating in the HOST Mode Configure Channel(n) to transmit an all "1's" pattern by writing to Command Register CR1-(n) and setting the TAOS_(n) bit-field (bit D3) to "1". COMMAND REGISTER CR1-(n)
D4 D3 D2 D1 D0
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n)
0
1
X
X
X
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE The XRT73L03A can command any channel to transmit an all "1's" pattern onto the line by toggling a single input pin or by setting a single bit-field within one of the Command Registers to "1".
NOTE: When this feature is activated, the Transmit Section of the configured channel overwrites the Terminal Equipment data with this all "1's" pattern.
Terminate the all "1's" pattern by writing to Command Register CR1-(n) and setting the TAOS_(n) bit-field (D3) to "0". 5.0 THE MICROPROCESSOR SERIAL INTERFACE The on-chip Command Registers of XRT73L03A DS3/E3/STS-1 Line Interface Unit IC are used to configure the XRT73L03A into a wide-variety of modes. This section discusses the following: 1. The description of the Command Registers. 2. A description on how to use the Microprocessor Serial Interface. 5.1 DESCRIPTION OF THE COMMAND REGISTERS (repeated as Table 7), lists the Command Registers, their Addresses and their bit-formats.
a. Operating in the Hardware Mode Configure Channel(n) to transmit an all "1's" pattern by toggling the TAOS_(n) input pin "High". Terminate the all "1's" pattern by toggling the TAOS_(n) input pin "Low".
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TABLE 7: HEXADECIMAL ADDRESSES AND BIT FORMATS OF XRT73L03A COMMAND REGISTERS
REGISTER BIT-FORMAT ADDRESS COMMAND REGISTER TYPE D4 D3 CHANNEL0 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 CR0-0 CR1-0 CR2-0 CR3-0 CR4-0 CR5-0 CR6-0 CR7-0 RO R/W R/W R/W R/W R/W R/W R/W RLOL_0 TxOFF_0 Reserved SR/(DR)_0 Reserved Reserved Reserved Reserved RLOS_0 TAOS_0 ENDECDIS_0 LOSMUT_0 STS-1/DS3_0 Reserved Reserved Reserved ALOS_0 TxClkINV_0 ALOSDIS_0 RxOFF_0 E3_0 Reserved Reserved Reserved DLOS_0 TxLEV_0 DLOSDIS_0 RxClk_0INV LLB_0 Reserved Reserved Reserved DMO_0 TxBIN_0 REQEN_0 Reserved RLB_0 Reserved Reserved Reserved D2 D1 D0
CHANNEL1 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F CR0-1 CR1-1 CR2-1 CR3-1 CR4-1 CR5-1 CR6-1 CR7-1 RO R/W R/W R/W R/W R/W R/W R/W RLOL_1 TxOFF_1 Reserved SR/(DR)_1 Reserved Reserved Reserved Reserved RLOS_1 TAOS_1 ENDECDIS_1 LOSMUT_1 STS-1/DS3_1 Reserved Reserved Reserved ALOS_1 TxClkINV_1 ALOSDIS_1 RxOFF_1 E3_1 Reserved Reserved Reserved DLOS_1 TxLEV_1 DLOSDIS_1 RxClk_1INV LLB_1 Reserved Reserved Reserved DMO_1 TxBIN_1 REQEN_1 Reserved RLB_1 Reserved Reserved Reserved
CHANNEL2 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 CR0-2 CR1-2 CR2-2 CR3-2 CR4-2 CR5-2 CR6-2 CR7-2 RO R/W R/W R/W R/W R/W R/W R/W RLOL_2 TxOFF_2 Reserved SR/(DR)_2 Reserved Reserved Reserved Reserved RLOS_2 TAOS_2 ENDECDIS_2 LOSMUT_2 STS-1/DS3_2 Reserved Reserved Reserved ALOS_2 TxClkINV_2 ALOSDIS_2 RxOFF_2 E3_2 Reserved Reserved Reserved DLOS_2 TxLEV_2 DLOSDIS_2 RxClk_2INV LLB_2 Reserved Reserved Reserved DMO_2 TxBIN_2 REQEN_2 Reserved RLB_2 Reserved Reserved Reserved
Address The register addresses are presented in the Hexadecimal format. Type: 53
The Command Registers are either Read-Only (RO) type of registers or Read/Write (R/W) type of registers. Each channel of the XRT73L03A has eight command registers, CR0-(n) through CR7-(n) where
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(n) = 0, 1 or 2. The associated addresses for each channel are presented in , (repeated as Table 7).
NOTE: The default value for each of the bit-fields within these register is "0".
This Read-Only bit-field indicates whether or not the Channel(n) Digital LOS Detector is currently declaring an LOS condition. This bit-field is set to "0" if the Channel(n) Digital LOS Detector is NOT currently declaring an LOS condition. This bit-field is set to "1" if the Channel(n) Digital LOS Detector is currently declaring an LOS condition.
NOTE: The purpose is to isolate the Detector (e.g., either the Analog LOS or the Digital LOS detector) that is declaring the LOS condition. This feature may be useful for troubleshooting/debugging purposes.
5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER 5.2.1 Command Register - CR0-(n) The bit-format and default values for Command Register CR0-(n) are listed below followed by the function of eah of these bit-fields. COMMAND REGISTER CR0-(n)
D4 D3 D2 D1 D0
Bit D0 - DMO_(n) (Drive Monitor Output Status Channel(n)) This Read-Only bit-field reflects the status of the DMO output pin. 5.2.2 Command Register CR1 The bit-format and default values for Command Register CR1-(n) are listed below followed by the function of each of these bit-fields.. COMMAND REGISTER CR1-(n)
D4 D3 D2 D1 D0
RLOL_(n) RLOS_(n) ALOS_(n) DLOS_(n) DMO_(n) 1 1 1 1 1
Bit D4 - RLOL_(n) (Receive Loss of Lock Status Channel(n)) This Read-Only bit-field reflects the lock status of the Channel(n) Clock Recovery Phase-Locked-Loop This bit-field is set to "0" if the Channel(n) Clock Recovery PLL is in lock with the incoming line signal. This bit-field is set to "1" if the Clock Recovery PLL is out of lock with the incoming line signal. Bit D3 - RLOS_(n) (Receive Loss of Signal Status Channel(n)) This Read-Only bit-field indicates whether or not the Channel(n) of the Receiver is currently declaring an LOS (Loss of Signal) Condition. This bit-field is set to "0" if Channel(n) is not currently declaring the LOS Condition. This bit-field is set to "1" if Channel(n) is declaring an LOS Condition. Bit D2 - ALOS_(n) (Analog Loss of Signal Status Channel(n)) This Read-Only bit-field indicates whether or not the Channel(n) Analog LOS Detector is currently declaring an LOS condition. This bit-field is set to "0" if the Analog LOS Detector within Channel(n) is NOT currently declaring an LOS condition. This bit-field is set to "1" if the Analog LOS Detector is currently declaring an LOS condition.
NOTE: The purpose is to isolate the Detector (e.g., either the Analog LOS or the Digital LOS detector) that is declaring the LOS condition. This feature may be useful for troubleshooting/debugging purposes
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n)
0
0
0
0
0
Bit D4 - TxOFF_(n) (Transmitter OFF - Channel(n)) This Read/Write bit-field is used to turn off the Channel(n) Transmitter. Writing a "1" to this bit field turns off the Transmitter and tri-state the Transmit Output. Writing a "0" to this bit-field turns on the Transmitter. Bit D3 - TAOS_(n) (Transmit All OneS - Channel(n)) This Read/Write bit-field is used to command the Channel(n) Transmitter to generate and transmit an all "1's" pattern onto the line. Writing a "1" to this bit-field commands the Transmitter to transmit an all "1's" pattern onto the line. Writing a "0" to this bit-field commands normal operation. Bit D2 - TxClkINV_(n) (Transmit Clock Invert Channel(n)) This Read/Write bit-field is used to configure the Transmitter to sample the signal at the TPData and TNData pins on the rising edge or falling edge of TxClk (the Transmit Line Clock signal). Writing a "1" to this bit-field configures the Transmitter to sample the TPData and TNData input pins on the rising edge of TxClk. Writing a "0" to this bit-field con-
Bit D1 - DLOS_(n) (Digital Loss of Signal Status Channel(n))
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figures the Transmitter to sample the TPData and TNData input pins on the falling edge of TxClk. Bit D1 - TxLEV_(n) (Transmit Line Build-Out Enable/Disable Select - Channel(n)) This Read/Write bit-field is used to enable or disable the Channel(n) Transmit Line Build-Out circuit. Setting this bit-field "High" disables the Channel(n) Line Build-Out circuit. In this mode, Channel(n) outputs partially-shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. Setting this bit-field "Low" enables the Channel(n) Line Build-Out circuit. In this mode, Channel(n) outputs shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. In order to comply with the Isolated DSX-3/STSX-1 Pulse Template Requiremnts per Bellcore GR-499CORE or GR-253-CORE:
a. Set this bit-field to "1" if the cable length between the Cross-Connect and the transmit output of Channel(n) is greater than 225 feet. b. Set this bit-field to "0" if the cable length between the Cross-Connect and the transmit output of Channel(n) is less than 225 feet. This bit-field is active only if the XRT73L03A is configured to operate in the DS3 or SONET STS-1 Modes. If the cable length is greater than 225 feet, set this bitfield to "1" in order to increase the amplitude of the Transmit Output Signal. If the cable length is less than 225 feet, set this bit-field to "0".
NOTE: This option is only available when the XRT73L03A is operating in the DS3 or STS-1 Mode.
5.2.3 Command Register CR2-(n) The bit-format and default values for Command Register CR2-(n) are listed below followed by the function of each of these bit fields.
COMMAND REGISTER CR2-(n)
D4 Reserved X D3 ENDECDIS_(n) 0 D2 ALOSDIS_(n) 0 D1 DLOSDIS_(n) 0 D0 REQEN_(n) 1
Bit D4 - Reserved Bit D3 - Reserved Bit D2 - ALOSDIS (Analog LOS Disable - Channel(n)) This Read/Write bit-field is used to enable or disable the Channel(n) Analog LOS Detector. Writing a "0" to this bit-field enables the Analog LOS Detector. Writing a "1" to this bit-field disables the Analog LOS Detector.
NOTE: If the Analog LOS Detector is disabled, then the RLOS input pin is only asserted by the DLOS (Digital LOS Detector).
Writing a "0" to this bit-field enables the Digital LOS Detector. Writing a "1" to this bit-field disables the Digital LOS Detector.
NOTE: If the Digital LOS Detector is disabled, then the RLOS input pin is only asserted by the ALOS (Analog LOS Detector).
Bit D0 - REQEN_(n) (Receive Equalization Enable - Channel(n)) This Read/Write bit-field is used to enable or disable the internal Channel(n) Receive Equalizer. Writing a "1" to this bit-field enables the Internal Equalizer. Writing a "0" to this bit-field disables the Internal Equalizer. 5.2.4 Command Register CR3-(n) The bit-format and default values for Command Register CR3-(n) are listed below followed by the function of each of these bit fields.
Bit D1 - DLOSDIS_(n) (Digital LOS Disable - Channel(n)) This Read/Write bit-field to used to enable or disable the Channel(n) Digital LOS Detector .
COMMAND REGISTER CR3-(n)
D4 SR/DR_(n) 0 D3 LOSMUT_(n) 1 D2 RxOFF_(n) 0 D1 RxClk_(n)INV 0 D0 Reserved 0
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Bit D4 - SR/DR_(n) (Single-Rail/Dual-Rail Data Output - Channel(n))/(B3ZS/HDB3 Encoder/Decoder-Disable - Channel(n)) This Read/Write bit-field is used to configure Channel(n) to output the received data from the Remote Terminal in a binary or Dual-Rail format and Enable or Disable the B3ZS/HDB3 Encoder and Decoder blocks. Writing a "1" to this bit-field enables the B3ZS/HDB3 Encoder and Decoder blocks. Writing a "0" to this bitfield disables the B3ZS/HDB3 Encoder and Decoder blocks.
NOTE: This Encoder/Decoder performs HDB3 Encoding/ Decoding if the XRT73L03A is operating in the E3 Mode. Otherwise, it performs B3ZS Encoding/Decoding.
RxClk_(n) output signal. Writing a "1" to this bit-field configures the Receiver to output the recovered data on the falling edge of the RxClk_(n) output signal. Bit D0 - Reserved This bit-field has no defined functionality Command Register CR4-(n) The bit-format and default values for Command Register CR4 are listed below followed by the function of each of these bit-fields. COMMAND REGISTER CR4-(n)
D4 D3 D2 E3_(n) 0 D1 D0
Reserved STS-1/DS3_(n) 0 0
LLB_(n) RLB_(n) 0 0
.Writing a "1" to this bit-field also configures Channel(n) to output data to the Terminal Equipment in a binary (Single-Rail) format via the RPOS_(n) output pin, RNEG_(n) is grounded. Writing a "0" to this bitfield configures Channel(n) to output data to the Terminal Equipment in a Dual-Rail format via both the RPOS_(n) and RNEG_(n) output pins. Bit D3 - LOSMUT_(n) (Recovered Data Muting, during LOS Condition - Channel(n)) This Read/Write bit-field is used to configure Channel(n) to not output any recovered data from the line while it is declaring an LOS condition. Writing a "0" to this bit-field configures the chip to output recovered data even while the XRT73L03A is declaring an LOS condition. Writing a "1" to this bit-field configures the chip to NOT output the recovered data while an LOS condition is being declared.
NOTE: In this mode, RPOS_(n) and RNEG_(n) is set to "0", asynchronously.
Bit D4 - Reserved This bit-field has no defined functionality Bit D3 - STS-1/(DS3_(n)) - Channel(n) - Mode Select This Read/Write bit field is used to configure Channel(n) to operate in either the SONET STS-1 Mode or the DS3 Mode. Writing a "0" into this bit-field configures Channel(n) to operate in the DS3 Mode. Writing a "1" into this bit-field configures Channel(n) to operate in the SONET STS-1 Mode.
NOTE: This bit-field is ignored if the E3_(n) bit-field (e.g., D2 within this Command Register) is set to "1".
Bit D2 - E3 Mode Select - Channel(n) This Read/Write bit-field is used to configure Channel(n) to operate in the E3 Mode. Writing a "0" into this bit-field configures Channel(n) to operate in either the DS3 or SONET STS-1 Mode as specified by the setting of the DS3 bit-field within this Command Register. Writing a "1" into this bitfield configures Channel(n) to operate in the E3 Mode. Bit D1 - LLB_(n) (Local Loop-Back - Channel(n)) This Read/Write bit-field along with RLB_(n) is used to configure Channel(n) to operate in any one of a variety of Loop-Back modes. Table 8 relates the contents of LLB_(n) and RLB_(n) and the corresponding Loop-Back mode for Channel(n). Bit D0 - RLB_(n) (Remote Loop-Back - Channel(n))
Bit D2 - RxOFF (Receive Section - Shut OFF Select) This Read/Write bit-field is used to shut-off the Receive Sections. The purpose is to conserve power consumption when this device is the back-up device in a Redundancy System. Writing a "1" into this bit-field shuts off the Receive Sections. Writing a "0" into this bit-field turns on the Receive Sections. Bit D1 - RxClk_(n)INV (Invert RxClk_(n)) This Read/Write bit-field is used to configure the Channel(n) Receiver to output the recovered data on either the rising edge or the falling edge of the RxClk_(n) clock signal. Writing a "0" to this bit-field configures the Receiver to output the recovered data on the rising edge of the
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This Read/Write bit-field, along with LLB_(n), is used to configure Channel(n) to operate in any one of a variety of Loop-Back modes.
Table 8 relates the contents of LLB_(n) and RLB_(n) and the corresponding Loop-Back mode for Channel(n).
TABLE 8: CONTENTS OF LLB_(n) AND RLB_(n) AND THE CORRESPONDING LOOP-BACK MODE FOR CHANNEL(n)
LLB_(n) 0 1 1 0 RLB_(n) 0 0 1 1 LOOP-BACK MODE (FOR CHANNEL(n)) None Analog Loop-Back Mode (See Section 4.1 for details) Digital Loop-Back Mode (See Section 4.2 for details) Remote Loop-Back Mode (See Section 4.3 for details)
5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. The XRT73L03A Serial Interface is a simple four wire interface that is compatible with many of the microcontrollers available in the market. This interface consists of the following signals: * CS - Chip Select (Active Low) * SClk - Serial Clock * SDI - Serial Data Input * SDO - Serial Data Output Using the Microprocessor Serial Interface The following instructions for using the Microprocessor Serial Interface are best understood by referring to the diagram in Figure 38 and the timing diagram in Figure 39. In order to use the Microprocessor Serial Interface, a clock signal must be first applied to the SClk input pin. Then, initiate a Read or Write operation by asserting the active-low Chip Select input pin CS. It is important to assert the CS pin (e.g., toggle it "Low") at least 5ns prior to the very first rising edge of the clock signal. Once the CS input pin has been asserted, the type of operation and the target register address must now be specified. Provide this information to the Microprocessor Serial Interface by writing eight serial bits of data into the SDI input.
NOTE: Each of these bits is clocked into the SDI input on the rising edge of SClk.
Bits 2 through 6: The five (5) bit Address Values (labeled A0, A1, A2 , A3 and A4) The next five rising edges of the SClk signal clocks in the 5-bit address value for this particular Read or Write operation. The address selects the Command Register in the XRT73L03A that the user is either reading data from or writing data to. The address bits must be supplied to the SDI input pin in ascending order with the LSB (least significant bit) first. Bit 7: A5 must be set to "0", as shown in Figure 38. Bit 8 - A6 The value of A6 is a don't care. Once these first 8 bits have been written into the Microprocessor Serial Interface, the subsequent action depends upon whether the current operation is a Read or Write operation. Read Operation Once the last address bit (A4) has been clocked into the SDI input, the Read operation proceeds through an idle period lasting two SClk periods. On the falling edge of SClk Cycle #8 (see Figure 38) the serial data output signal (SDO) becomes active. At this point, reading the data contents of the addressed Command Register at Address [A4, A3, A2, A1, A0] via the SDO output pin can begin. The Microprocessor Serial Interface outputs this five bit data word (D0 through D4) in ascending order with the LSB first on the falling edges of the SClk pin. Consequently, the data on the SDO output pin is sufficiently stable for reading by the Microprocessor on the very next rising edge of the SClk pin. Write Operation Once the last address bit (A4) has been clocked into the SDI input, the Write operation proceeds through an idle period lasting two SClk periods. Prior to the rising edge of SClk Cycle # 9 (see Figure 38). Apply 57
Bit 1 - R/W (Read/Write) Bit This bit is clocked into the SDI input, on the first rising edge of SClk after CS has been asserted. This bit indicates whether the current operation is a Read or Write operation. A "1" in this bit specifies a Read operation, a "0" in this bit specifies a Write operation.
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
the desired eight bit data word to the SDI input pin via the Microprocessor Serial Interface. The Microprocessor Serial Interface latches the value on the SDI input pin on the rising edge of SClk. Apply this word (D0 through D7) serially, in ascending order with the LSB first. Simplified Interface Option The design of the circuitry connecting to the Microprocessor Serial Interface can be simplified by tying both the SDO and SDI pins together and reading data
from and/or writing data to this combined signal. This simplification is possible because only one of these signals are active at any given time. The inactive signal is tri-stated.
NOTES: 1. 2. 3. 4. A5 is always "0" R/W = "1" for Read Operations R/W = "0" for Write Operations Shaded box denotes a "don't care" value
FIGURE 38. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS SClk SDI SDO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A0
A1
A2
A3
A4
0
A6
D0
D1
D2
D3
D4
D5
D6
D7
High Z
D0 D1 D2 D3 D4 0 0 0
High Z
FIGURE 39. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29 CS t22 SClk t23 SDI t24 R/W A0 A1 t25 t21 t27 t26 t28
CS
SClk t30 SDO Hi-Z D0 t31 D1 Hi-Z t33 D2 D7 t32
SDI
58
XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
ORDERING INFORMATION
PART # XRT73L03AIV THERMAL INFORMATION PACKAGE 120 Pin Thermally Enhanced TQFP 14mm X 20mm Theta-JA = 23 C/W OPERATING TEMPERATURE RANGE -40oC to +85oC Theta-JC =7 C/W
PACKAGE DIMENSIONS
120 LEAD THIN QUAD FLAT PACK 14mm X 20 mm, TQFP
Rev. 1.00
D D1 96 61
97
60
Copper Heat slug OFHC 0.9999 solder plated exposed on package bottom E1 E
120
37
A2
1 e B
36
A C A1 SYMBOL A A1 A2 B C D D1 E E1 e L INCHES MIN MAX 0.055 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.004 0.008 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020BSC 0.018 0.030 0o 0.370 7o 0.390 MILLIMETERS MIN 1.40 0.05 1.35 0.17 0.09 21.80 19.90 15.80 13.90 0.50BSC 0.45 0o 9.40 0.75 7o 9.90 MAX 1.60 0.15 1.45 0.27 0.20 22.20 20.10 16.20 14.10 L
Note: The control dimension is the millimeter column
59
XRT73L03A
REVISION HISTORY REV #
2.0.0 DATE
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
CHANGES MADE
December 2001 Original XRT73L03A. Redesigned 73L03 with improved performance and added
timing recovery circuit. Added typical E3 Jitter tolerance @800kHz. Receiver Sensitivity (cable length) increased. Updated Transformer Recommendations.
2.0.1 2.0.2 2.0.3 2.0.4 February 2002 July 2002 August 2002 October 2003
Added connection points to various drawings.
Page 30, sect. 2.3.3. (a)., changed encoder/decoder disable to "1". Page 57 ......."toggle CS "Low" 5ns (from 50ns) prior to first rising edge of the clock....." Changed the default register setting for REQEN_(n) in CR2.
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet October 2003. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 60

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